diff options
| author | Jesse Barnes <jesse.barnes@intel.com> | 2007-08-03 20:40:45 -0700 |
|---|---|---|
| committer | Jesse Barnes <jesse.barnes@intel.com> | 2007-08-03 20:40:45 -0700 |
| commit | 3d3c0e8c55f639a501c0756948b518abd903d7d0 (patch) | |
| tree | d43002abbaf2829e2a6a979f17b32ef2f13760eb /src/i830_reg.h | |
| parent | 0da4f2b0cd7203377ad10407928a367b8c6d310e (diff) | |
Tiled rendering & fbc fixes:
- actually enable tiling in DSP(A|B)CNTR if needed
- add logic to EXA routines for tiled case (still needs work)
- enable/disable fbc on DPMS events (meant moving functions higher in file)
- fix fence register pitch programming (use correct pitch instead of kludged value)
Diffstat (limited to 'src/i830_reg.h')
| -rw-r--r-- | src/i830_reg.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/i830_reg.h b/src/i830_reg.h index 8a2a98ac..df22ed41 100644 --- a/src/i830_reg.h +++ b/src/i830_reg.h @@ -36,6 +36,7 @@ #define FBC_CTL_EN (1<<31) #define FBC_CTL_PERIODIC (1<<30) #define FBC_CTL_INTERVAL_SHIFT (16) +#define FBC_CTL_UNCOMPRESSIBLE (1<<14) #define FBC_CTL_STRIDE_SHIFT (5) #define FBC_CTL_FENCENO (1<<0) #define FBC_COMMAND 0x0320c @@ -46,9 +47,15 @@ #define FBC_STAT_MODIFIED (1<<29) #define FBC_STAT_CURRENT_LINE (1<<0) #define FBC_CONTROL2 0x03214 +#define FBC_CTL_FENCE_DBL (0<<4) +#define FBC_CTL_IDLE_IMM (0<<2) +#define FBC_CTL_IDLE_FULL (1<<2) +#define FBC_CTL_IDLE_LINE (2<<2) +#define FBC_CTL_IDLE_DEBUG (3<<2) #define FBC_CTL_CPU_FENCE (1<<1) #define FBC_CTL_PLANEA (0<<0) #define FBC_CTL_PLANEB (1<<0) +#define FBC_FENCE_OFF 0x0321b #define FBC_LL_SIZE (1536) #define FBC_LL_PAD (32) |