diff options
| author | Zhenyu Wang <zhenyu.z.wang@intel.com> | 2007-11-15 18:33:27 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyu.z.wang@intel.com> | 2007-11-15 18:33:27 +0800 |
| commit | 6f3de19159cd7a2d73ed212add909edb3aedce9c (patch) | |
| tree | 364839d798b3d689d16e831451c61f8a9f7180c8 /src/i830_reg.h | |
| parent | e64f4929690a57701241334fbca17e95b39ba3d4 (diff) | |
Move fb compression reg definition into i810_reg.h
where we put MMIO control reg in, and shared with intel_reg_dump
program.
Diffstat (limited to 'src/i830_reg.h')
| -rw-r--r-- | src/i830_reg.h | 33 |
1 files changed, 0 insertions, 33 deletions
diff --git a/src/i830_reg.h b/src/i830_reg.h index 4d7736a8..7a8df9f8 100644 --- a/src/i830_reg.h +++ b/src/i830_reg.h @@ -29,39 +29,6 @@ #ifndef _I830_REG_H_ #define _I830_REG_H_ -/* Framebuffer compression */ -#define FBC_CFB_BASE 0x03200 /* 4k page aligned */ -#define FBC_LL_BASE 0x03204 /* 4k page aligned */ -#define FBC_CONTROL 0x03208 -#define FBC_CTL_EN (1<<31) -#define FBC_CTL_PERIODIC (1<<30) -#define FBC_CTL_INTERVAL_SHIFT (16) -#define FBC_CTL_UNCOMPRESSIBLE (1<<14) -#define FBC_CTL_STRIDE_SHIFT (5) -#define FBC_CTL_FENCENO (1<<0) -#define FBC_COMMAND 0x0320c -#define FBC_CMD_COMPRESS (1<<0) -#define FBC_STATUS 0x03210 -#define FBC_STAT_COMPRESSING (1<<31) -#define FBC_STAT_COMPRESSED (1<<30) -#define FBC_STAT_MODIFIED (1<<29) -#define FBC_STAT_CURRENT_LINE (1<<0) -#define FBC_CONTROL2 0x03214 -#define FBC_CTL_FENCE_DBL (0<<4) -#define FBC_CTL_IDLE_IMM (0<<2) -#define FBC_CTL_IDLE_FULL (1<<2) -#define FBC_CTL_IDLE_LINE (2<<2) -#define FBC_CTL_IDLE_DEBUG (3<<2) -#define FBC_CTL_CPU_FENCE (1<<1) -#define FBC_CTL_PLANEA (0<<0) -#define FBC_CTL_PLANEB (1<<0) -#define FBC_FENCE_OFF 0x0321b -#define FBC_MOD_NUM 0x03220 -#define FBC_TAG_DEBUG 0x03300 - -#define FBC_LL_SIZE (1536) -#define FBC_LL_PAD (32) - #define I830_SET_FIELD( var, mask, value ) (var &= ~(mask), var |= value) #define CMD_3D (0x3<<29) |