diff options
| author | Wang Zhenyu <zhenyu.z.wang@intel.com> | 2006-07-21 00:56:58 +0800 |
|---|---|---|
| committer | Wang Zhenyu <zhenyu.z.wang@intel.com> | 2006-07-21 00:56:58 +0800 |
| commit | a7e30bb051bc03063fe699473610a57054a64973 (patch) | |
| tree | 4fcbdbc5eaa6d0ca093c813f6ee05a0b8aa42aca /src/i830_reg.h | |
| parent | ac34a37cb60d763cbd99b6e2f6fdcb639592b99b (diff) | |
Take from i915, blend ctl code cleanup.
Diffstat (limited to 'src/i830_reg.h')
| -rw-r--r-- | src/i830_reg.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/i830_reg.h b/src/i830_reg.h index ae68a2e9..f9c1df9f 100644 --- a/src/i830_reg.h +++ b/src/i830_reg.h @@ -221,6 +221,22 @@ #define ENABLE_DST_ABLEND_FACTOR (1<<5) #define DST_ABLEND_FACT(x) (x) +#define BLENDFACTOR_ZERO 0x01 +#define BLENDFACTOR_ONE 0x02 +#define BLENDFACTOR_SRC_COLR 0x03 +#define BLENDFACTOR_INV_SRC_COLR 0x04 +#define BLENDFACTOR_SRC_ALPHA 0x05 +#define BLENDFACTOR_INV_SRC_ALPHA 0x06 +#define BLENDFACTOR_DST_ALPHA 0x07 +#define BLENDFACTOR_INV_DST_ALPHA 0x08 +#define BLENDFACTOR_DST_COLR 0x09 +#define BLENDFACTOR_INV_DST_COLR 0x0a +#define BLENDFACTOR_SRC_ALPHA_SATURATE 0x0b +#define BLENDFACTOR_CONST_COLOR 0x0c +#define BLENDFACTOR_INV_CONST_COLOR 0x0d +#define BLENDFACTOR_CONST_ALPHA 0x0e +#define BLENDFACTOR_INV_CONST_ALPHA 0x0f +#define BLENDFACTOR_MASK 0x0f /* _3DSTATE_MAP_BLEND_ARG, p152 */ #define _3DSTATE_MAP_BLEND_ARG_CMD(stage) (CMD_3D|(0x0e<<24)|((stage)<<20)) |