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authorWang Zhenyu <zhenyu.z.wang@intel.com>2007-04-20 10:54:34 +0800
committerWang Zhenyu <zhenyu.z.wang@intel.com>2007-04-20 10:54:34 +0800
commitcebdb8bfc6170a0fb441039f4422917fd0c77e70 (patch)
tree43ad4497d02b57e4060d0362f77983ae99550c25 /src/i830_render.c
parentcca389769001c657435f056e1f1c26b0f52a48bd (diff)
EXA: set enabling bits properly for i830
This was found when debug exa on a 865GV, we should set pipeline state bits properly, otherwise the engine will hang.
Diffstat (limited to 'src/i830_render.c')
-rw-r--r--src/i830_render.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/src/i830_render.c b/src/i830_render.c
index 36d41f3c..077afa1a 100644
--- a/src/i830_render.c
+++ b/src/i830_render.c
@@ -515,9 +515,16 @@ i830_prepare_composite(int op, PicturePtr pSrcPicture,
OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(8) | 0);
OUT_RING(S8_ENABLE_COLOR_BLEND | S8_BLENDFUNC_ADD | blendctl |
S8_ENABLE_COLOR_BUFFER_WRITE);
+
+ OUT_RING(_3DSTATE_ENABLES_1_CMD | DISABLE_LOGIC_OP |
+ DISABLE_STENCIL_TEST | DISABLE_DEPTH_BIAS |
+ DISABLE_SPEC_ADD | DISABLE_FOG | DISABLE_ALPHA_TEST |
+ ENABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
/* We have to explicitly say we don't want write disabled */
- OUT_RING(_3DSTATE_ENABLES_2_CMD | ENABLE_COLOR_MASK);
- OUT_RING(MI_NOOP);
+ OUT_RING(_3DSTATE_ENABLES_2_CMD | ENABLE_COLOR_MASK |
+ DISABLE_STENCIL_WRITE | ENABLE_TEX_CACHE |
+ DISABLE_DITHER | ENABLE_COLOR_WRITE |
+ DISABLE_DEPTH_WRITE);
ADVANCE_LP_RING();
}