uxa: Limit maximum size of tiled objects

On older chipsets (i.e. pre-i965) tiling is very restrictive and imposes
severe size and alignment constraints. Combine that with relatively
small apertures and it is very easy to create a batch buffer that
cannot be mapped into the aperture (but would otherwise fit based purely
on total object size). To prevent this we need to not use tiling for large
buffers (the very same buffers where tiling would be of most benefit!).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

1 files changed, 6 insertions, 0 deletions

diff --git a/src/i830_uxa.c b/src/i830_uxa.c
index 89da5d00..801c2c77 100644
--- a/src/i830_uxa.c
+++ b/src/i830_uxa.c
@@ -138,6 +138,7 @@ i830_uxa_pixmap_compute_size(PixmapPtr pixmap,
 			*tiling = I915_TILING_NONE;
 	}
 
+  repeat:
 	if (*tiling == I915_TILING_NONE) {
 		pitch_align = intel->accel_pixmap_pitch_alignment;
 	} else {
@@ -171,6 +172,11 @@ i830_uxa_pixmap_compute_size(PixmapPtr pixmap,
 		assert(size >= *stride * aligned_h);
 	}
 
+	if (*tiling != I915_TILING_NONE && size > intel->max_tiling_size) {
+		*tiling = I915_TILING_NONE;
+		goto repeat;
+	}
+
 	return size;
 }