diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2009-11-30 20:50:31 +0000 |
|---|---|---|
| committer | Owain G. Ainsworth <oga@openbsd.org> | 2010-03-01 18:46:46 +0000 |
| commit | 9d48d56fcf634b8bee3a7d45d47543abf03b7a32 (patch) | |
| tree | cbd62c38283ef8d98e60fb9e5b25fb689696f684 /src/i830_uxa.c | |
| parent | 8b50cae70dc926ce3416466d0cb6516d3d4a6002 (diff) | |
uxa: Limit maximum size of tiled objects
On older chipsets (i.e. pre-i965) tiling is very restrictive and imposes
severe size and alignment constraints. Combine that with relatively
small apertures and it is very easy to create a batch buffer that
cannot be mapped into the aperture (but would otherwise fit based purely
on total object size). To prevent this we need to not use tiling for large
buffers (the very same buffers where tiling would be of most benefit!).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
(cherry picked from commit 00aa4f7a45a318af5b651f9f3928e9da4443233a)
Signed-off-by: Owain G. Ainsworth <oga@openbsd.org>
Diffstat (limited to 'src/i830_uxa.c')
| -rw-r--r-- | src/i830_uxa.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/i830_uxa.c b/src/i830_uxa.c index 83074c88..424a0a56 100644 --- a/src/i830_uxa.c +++ b/src/i830_uxa.c @@ -138,6 +138,7 @@ i830_uxa_pixmap_compute_size(PixmapPtr pixmap, *tiling = I915_TILING_NONE; } + repeat: if (*tiling == I915_TILING_NONE) { pitch_align = intel->accel_pixmap_pitch_alignment; } else { @@ -171,6 +172,11 @@ i830_uxa_pixmap_compute_size(PixmapPtr pixmap, assert(size >= *stride * aligned_h); } + if (*tiling != I915_TILING_NONE && size > intel->max_tiling_size) { + *tiling = I915_TILING_NONE; + goto repeat; + } + return size; } |