diff options
| author | Keith Packard <keithp@keithp.com> | 2009-07-10 17:13:14 -0700 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2009-07-10 18:26:59 -0700 |
| commit | ed8a9a94e1a670ca35311c9ed83d0c479530d41a (patch) | |
| tree | a8b193424caf6195e26a759f102d62a5b3c4415c /src/i830_uxa.c | |
| parent | cb19ac207b784d814f6f389110fd1b21a0f34e8b (diff) | |
i830_uxa_prepare_access: Flush and wait for idle for non-bo pixmaps
Without kernel support and explicit knowledge about where in the ring the
last rendering operation for a specific pixmap was, we must synchronize with
any outstanding rendering before accessing a pixmap which does not have a
buffer object.
Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'src/i830_uxa.c')
| -rw-r--r-- | src/i830_uxa.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/src/i830_uxa.c b/src/i830_uxa.c index c3fdcec5..2050c485 100644 --- a/src/i830_uxa.c +++ b/src/i830_uxa.c @@ -477,13 +477,12 @@ static Bool i830_uxa_prepare_access (PixmapPtr pixmap, uxa_access_t access) { dri_bo *bo = i830_get_pixmap_bo (pixmap); + ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum]; + + intel_batch_flush(scrn, FALSE); if (bo) { - ScreenPtr screen = pixmap->drawable.pScreen; - ScrnInfoPtr scrn = xf86Screens[screen->myNum]; I830Ptr i830 = I830PTR(scrn); - - intel_batch_flush(scrn, FALSE); /* No VT sema or GEM? No GTT mapping. */ if (!scrn->vtSema || !i830->have_gem) { @@ -517,7 +516,9 @@ i830_uxa_prepare_access (PixmapPtr pixmap, uxa_access_t access) drm_intel_gem_bo_start_gtt_access(bo, access == UXA_ACCESS_RW); pixmap->devPrivate.ptr = i830->FbBase + bo->offset; } - } + } else + i830_wait_ring_idle(scrn); + return TRUE; } |