diff options
| author | Eric Anholt <eric@anholt.net> | 2008-03-14 10:04:18 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2008-03-14 10:18:11 -0700 |
| commit | 69fbc17441d0f894d17b058e65ae22300cd2a54c (patch) | |
| tree | 5c1c2e0830dfef2bf9577b10ec4b6162c78b16aa /src/i915_3d.c | |
| parent | 65f92cfb7a05c9c028cf73ce1221cc0a651b50b3 (diff) | |
Change OUT_RING and similar calls to OUT_BATCH for batchbuffer merge
Diffstat (limited to 'src/i915_3d.c')
| -rw-r--r-- | src/i915_3d.c | 66 |
1 files changed, 33 insertions, 33 deletions
diff --git a/src/i915_3d.c b/src/i915_3d.c index ff591716..b2dbeed4 100644 --- a/src/i915_3d.c +++ b/src/i915_3d.c @@ -38,32 +38,32 @@ void I915EmitInvarientState( ScrnInfoPtr pScrn ) { I830Ptr pI830 = I830PTR(pScrn); - BEGIN_LP_RING(24); + BEGIN_BATCH(24); - OUT_RING(_3DSTATE_AA_CMD | + OUT_BATCH(_3DSTATE_AA_CMD | AA_LINE_ECAAR_WIDTH_ENABLE | AA_LINE_ECAAR_WIDTH_1_0 | AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0); /* Disable independent alpha blend */ - OUT_RING(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD | - IAB_MODIFY_ENABLE | - IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) | - IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE << IAB_SRC_FACTOR_SHIFT) | - IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO << IAB_DST_FACTOR_SHIFT)); + OUT_BATCH(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD | + IAB_MODIFY_ENABLE | + IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) | + IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE << IAB_SRC_FACTOR_SHIFT) | + IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO << IAB_DST_FACTOR_SHIFT)); - OUT_RING(_3DSTATE_DFLT_DIFFUSE_CMD); - OUT_RING(0); + OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD); + OUT_BATCH(0); - OUT_RING(_3DSTATE_DFLT_SPEC_CMD); - OUT_RING(0); + OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD); + OUT_BATCH(0); - OUT_RING(_3DSTATE_DFLT_Z_CMD); - OUT_RING(0); + OUT_BATCH(_3DSTATE_DFLT_Z_CMD); + OUT_BATCH(0); /* Don't support texture crossbar yet */ - OUT_RING(_3DSTATE_COORD_SET_BINDINGS | + OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS | CSB_TCB(0, 0) | CSB_TCB(1, 1) | CSB_TCB(2, 2) | @@ -73,7 +73,7 @@ void I915EmitInvarientState( ScrnInfoPtr pScrn ) CSB_TCB(6, 6) | CSB_TCB(7, 7)); - OUT_RING(_3DSTATE_RASTER_RULES_CMD | + OUT_BATCH(_3DSTATE_RASTER_RULES_CMD | ENABLE_POINT_RASTER_RULE | OGL_POINT_RASTER_RULE | ENABLE_LINE_STRIP_PROVOKE_VRTX | @@ -83,29 +83,29 @@ void I915EmitInvarientState( ScrnInfoPtr pScrn ) ENABLE_TEXKILL_3D_4D | TEXKILL_4D); - OUT_RING(_3DSTATE_MODES_4_CMD | - ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) | - ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) | - ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff)); + OUT_BATCH(_3DSTATE_MODES_4_CMD | + ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) | + ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) | + ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff)); - OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | 0); - OUT_RING(0x00000000); /* Disable texture coordinate wrap-shortest */ + OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | 0); + OUT_BATCH(0x00000000); /* Disable texture coordinate wrap-shortest */ - OUT_RING(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT); - OUT_RING(_3DSTATE_SCISSOR_RECT_0_CMD); - OUT_RING(0); - OUT_RING(0); + OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT); + OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD); + OUT_BATCH(0); + OUT_BATCH(0); - OUT_RING(_3DSTATE_DEPTH_SUBRECT_DISABLE); + OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE); - OUT_RING(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */ - OUT_RING(0); + OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */ + OUT_BATCH(0); - OUT_RING(_3DSTATE_STIPPLE); - OUT_RING(0x00000000); + OUT_BATCH(_3DSTATE_STIPPLE); + OUT_BATCH(0x00000000); - OUT_RING(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0 ); - OUT_RING(MI_NOOP); + OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0 ); + OUT_BATCH(MI_NOOP); - ADVANCE_LP_RING(); + ADVANCE_BATCH(); } |