diff options
| author | Eric Anholt <eric@anholt.net> | 2007-08-10 14:16:59 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2007-08-10 16:33:04 -0700 |
| commit | cb36635a053d4ac3971fea05060d31dbd3d382d2 (patch) | |
| tree | 80148e2a55a9c01fe85334789fc285339b16b8c4 /src/i915_render.c | |
| parent | ed1b106fabf3a18489bdb3083326f27387a9cb72 (diff) | |
Attempt to fix several front buffer tiling failure cases.
Front buffer tiling is now disabled with G965 and XAA. Some of the acceleration
that i830_xaa.c does can't be supported on tiled buffers.
Adds a tiling field to struct i830_memory, and uses it instead of separate
variables for each potential tiled buffer.
Diffstat (limited to 'src/i915_render.c')
| -rw-r--r-- | src/i915_render.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/i915_render.c b/src/i915_render.c index 9c937f23..7f25d90a 100644 --- a/src/i915_render.c +++ b/src/i915_render.c @@ -285,10 +285,9 @@ i915_texture_setup(PicturePtr pPict, PixmapPtr pPix, int unit) pI830->mapstate[unit * 3 + 0] = offset; pI830->mapstate[unit * 3 + 1] = format | + MS3_USE_FENCE_REGS | ((pPix->drawable.height - 1) << MS3_HEIGHT_SHIFT) | ((pPix->drawable.width - 1) << MS3_WIDTH_SHIFT); - if (pI830->tiling) - pI830->mapstate[unit * 3 + 1] |= MS3_USE_FENCE_REGS; pI830->mapstate[unit * 3 + 2] = ((pitch / 4) - 1) << MS4_PITCH_SHIFT; pI830->samplerstate[unit * 3 + 0] = (MIPFILTER_NONE << |