diff options
| author | Gwenole Beauchesne <gwenole.beauchesne@intel.com> | 2012-05-04 17:09:19 +0200 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2012-08-03 12:20:18 +0100 |
| commit | ce4421e175ceb9259208c7c223af8d66282c3db3 (patch) | |
| tree | 3b2ba0ff7a3c95a8add569b0d00454b678087b8c /src/i965_3d.c | |
| parent | 8c880aa34c522b0d67cbb932771f00c947d00dec (diff) | |
uxa: use at least 64 URB entries for Haswell
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/i965_3d.c')
| -rw-r--r-- | src/i965_3d.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/i965_3d.c b/src/i965_3d.c index d4d38e59..a18db125 100644 --- a/src/i965_3d.c +++ b/src/i965_3d.c @@ -104,12 +104,17 @@ gen6_upload_urb(intel_screen_private *intel) void gen7_upload_urb(intel_screen_private *intel) { + unsigned int num_urb_entries = 32; + + if (IS_HSW(intel)) + num_urb_entries = 64; + OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2)); OUT_BATCH(8); /* in 1KBs */ OUT_BATCH(GEN7_3DSTATE_URB_VS | (2 - 2)); OUT_BATCH( - (32 << GEN7_URB_ENTRY_NUMBER_SHIFT) | /* at least 32 */ + (num_urb_entries << GEN7_URB_ENTRY_NUMBER_SHIFT) | (2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT | (1 << GEN7_URB_STARTING_ADDRESS_SHIFT)); |