diff options
| author | Gwenole Beauchesne <gwenole.beauchesne@intel.com> | 2012-05-04 17:17:22 +0200 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2012-08-03 12:20:23 +0100 |
| commit | a47ba68996f117fabcb601d35bcc5f99cbcd6122 (patch) | |
| tree | 2229a4fb39d8716f0af1d739312c4258094bcdce /src/i965_reg.h | |
| parent | ce4421e175ceb9259208c7c223af8d66282c3db3 (diff) | |
uxa: fix max PS threads shift value for Haswell
The maximum number of threads is now a 9-bit value. Thus, one more bit
towards LSB was re-used. i.e. bit position is now 23 instead of 24 on
Ivy Bridge.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/i965_reg.h')
| -rw-r--r-- | src/i965_reg.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/i965_reg.h b/src/i965_reg.h index e7b0d15d..45b6d082 100644 --- a/src/i965_reg.h +++ b/src/i965_reg.h @@ -219,7 +219,8 @@ # define GEN7_PS_FLOATING_POINT_MODE_ALT (1 << 16) /* DW3: scratch space */ /* DW4 */ -# define GEN7_PS_MAX_THREADS_SHIFT 24 +# define GEN7_PS_MAX_THREADS_SHIFT_IVB 24 +# define GEN7_PS_MAX_THREADS_SHIFT_HSW 23 # define GEN7_PS_PUSH_CONSTANT_ENABLE (1 << 11) # define GEN7_PS_ATTRIBUTE_ENABLE (1 << 10) # define GEN7_PS_OMASK_TO_RENDER_TARGET (1 << 9) |