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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2009-11-10 11:05:20 +0000 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2009-11-10 15:19:08 +0000 |
| commit | 67af5a99253b1295f8dc09b28863eb7dc8b59e1d (patch) | |
| tree | a434b1f310c45d00affad115ede2ae92708d5a83 /src/i965_render.c | |
| parent | 998d6b3d8c549086fbc8a9f0e309694b23398d8d (diff) | |
Check that batch buffers are atomic.
Since batch buffers are rarely emitted by themselves but as part of a
sequence of state and vertices, the whole sequence is emitted atomically.
Here we just enforce that batches are marked as being part of an atomic
sequence as appropriate.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'src/i965_render.c')
| -rw-r--r-- | src/i965_render.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/i965_render.c b/src/i965_render.c index 09a71bf4..236ce497 100644 --- a/src/i965_render.c +++ b/src/i965_render.c @@ -1158,7 +1158,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn) * rendering pipe */ { - BEGIN_BATCH(2); + ATOMIC_BATCH(2); OUT_BATCH(MI_FLUSH | MI_STATE_INSTRUCTION_CACHE_FLUSH | BRW_MI_GLOBAL_SNAPSHOT_RESET); @@ -1167,9 +1167,9 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn) } { if (IS_IGDNG(intel)) - BEGIN_BATCH(14); + ATOMIC_BATCH(14); else - BEGIN_BATCH(12); + ATOMIC_BATCH(12); /* Match Mesa driver setup */ if (IS_G4X(intel) || IS_IGDNG(intel)) @@ -1215,7 +1215,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn) } { int pipe_ctrl; - BEGIN_BATCH(26); + ATOMIC_BATCH(26); /* Pipe control */ if (IS_IGDNG(intel)) @@ -1328,7 +1328,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn) } if (IS_IGDNG(intel)) { - BEGIN_BATCH(mask ? 9 : 7); + ATOMIC_BATCH(mask ? 9 : 7); /* * The reason to add this extra vertex element in the header is that * IGDNG has different vertex header definition and origin method to @@ -1358,7 +1358,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn) (BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT)); } else { - BEGIN_BATCH(mask ? 7 : 5); + ATOMIC_BATCH(mask ? 7 : 5); /* Set up our vertex elements, sourced from the single vertex buffer. * that will be set up later. */ @@ -1804,7 +1804,7 @@ i965_composite(PixmapPtr dest, int srcX, int srcY, int maskX, int maskY, if (intel->needs_render_state_emit) i965_emit_composite_state(scrn); - BEGIN_BATCH(12); + ATOMIC_BATCH(12); OUT_BATCH(MI_FLUSH); /* Set up the pointer to our (single) vertex buffer */ OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | 3); |