diff options
| author | Gwenole Beauchesne <gwenole.beauchesne@intel.com> | 2012-05-04 18:26:46 +0200 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2012-08-03 12:20:29 +0100 |
| commit | 4cd9ec9d404d934268952a1058afa07741b09efe (patch) | |
| tree | 17bd730798e692c323159cda23de585a5f9fa195 /src/i965_render.c | |
| parent | 412668464cf9505629eac20001701af3402dc6e8 (diff) | |
uxa: fix 3DSTATE_PS to fill in number of samples for Haswell
The sample mask value must match what is set for 3DSTATE_SAMPLE_MASK,
through gen6_upload_invariant_states().
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/i965_render.c')
| -rw-r--r-- | src/i965_render.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/i965_render.c b/src/i965_render.c index f7b21c8b..42b19599 100644 --- a/src/i965_render.c +++ b/src/i965_render.c @@ -2695,9 +2695,11 @@ gen7_composite_wm_state(intel_screen_private *intel, { int num_surfaces = has_mask ? 3 : 2; unsigned int max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_IVB; + unsigned int num_samples = 0; if (IS_HSW(intel)) { max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_HSW; + num_samples = 1 << GEN7_PS_SAMPLE_MASK_SHIFT_HSW; } if (intel->gen6_render_state.kernel == bo) @@ -2715,7 +2717,7 @@ gen7_composite_wm_state(intel_screen_private *intel, OUT_BATCH((1 << GEN7_PS_SAMPLER_COUNT_SHIFT) | (num_surfaces << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); OUT_BATCH(0); /* scratch space base offset */ - OUT_BATCH(((48 - 1) << max_threads_shift) | + OUT_BATCH(((48 - 1) << max_threads_shift) | num_samples | GEN7_PS_ATTRIBUTE_ENABLE | GEN7_PS_16_DISPATCH_ENABLE); OUT_BATCH((6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0)); |