Naming and formatting cleanup in Render acceleration code.

1 files changed, 476 insertions, 448 deletions

diff --git a/src/i965_render.c b/src/i965_render.c
index 99bd6284..5ff174da 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -52,12 +52,9 @@ do {							\
 #define I830FALLBACK(s, arg...) 			\
 do { 							\
 	return FALSE;					\
-} while(0) 
+} while(0)
 #endif
 
-static void I965GetBlendCntl(int op, PicturePtr pMask, CARD32 dst_format, 
-			     CARD32 *sblend, CARD32 *dblend);
-
 struct blendinfo {
     Bool dst_alpha;
     Bool src_alpha;
@@ -73,7 +70,7 @@ struct formatinfo {
 // refer vol2, 3d rasterization 3.8.1
 
 /* defined in brw_defines.h */
-static struct blendinfo I965BlendOp[] = { 
+static struct blendinfo i965_blend_op[] = {
     /* Clear */
     {0, 0, BRW_BLENDFACTOR_ZERO,          BRW_BLENDFACTOR_ZERO},
     /* Src */
@@ -102,28 +99,30 @@ static struct blendinfo I965BlendOp[] = {
     {0, 0, BRW_BLENDFACTOR_ONE,           BRW_BLENDFACTOR_ONE},
 };
 
-/* FIXME: surface format defined in brw_defines.h, shared Sampling engine 1.7.2*/
-static struct formatinfo I965TexFormats[] = {
-        {PICT_a8r8g8b8, BRW_SURFACEFORMAT_B8G8R8A8_UNORM },
-        {PICT_x8r8g8b8, BRW_SURFACEFORMAT_B8G8R8X8_UNORM },
-        {PICT_a8b8g8r8, BRW_SURFACEFORMAT_R8G8B8A8_UNORM },
-        {PICT_x8b8g8r8, BRW_SURFACEFORMAT_R8G8B8X8_UNORM },
-        {PICT_r5g6b5,   BRW_SURFACEFORMAT_B5G6R5_UNORM   },
-        {PICT_a1r5g5b5, BRW_SURFACEFORMAT_B5G5R5A1_UNORM },
-        {PICT_a8,       BRW_SURFACEFORMAT_A8_UNORM	 },
+/* FIXME: surface format defined in brw_defines.h, shared Sampling engine
+ * 1.7.2
+ */
+static struct formatinfo i965_tex_formats[] = {
+    {PICT_a8r8g8b8, BRW_SURFACEFORMAT_B8G8R8A8_UNORM },
+    {PICT_x8r8g8b8, BRW_SURFACEFORMAT_B8G8R8X8_UNORM },
+    {PICT_a8b8g8r8, BRW_SURFACEFORMAT_R8G8B8A8_UNORM },
+    {PICT_x8b8g8r8, BRW_SURFACEFORMAT_R8G8B8X8_UNORM },
+    {PICT_r5g6b5,   BRW_SURFACEFORMAT_B5G6R5_UNORM   },
+    {PICT_a1r5g5b5, BRW_SURFACEFORMAT_B5G5R5A1_UNORM },
+    {PICT_a8,       BRW_SURFACEFORMAT_A8_UNORM	 },
 };
 
-static void I965GetBlendCntl(int op, PicturePtr pMask, CARD32 dst_format, 
-			     CARD32 *sblend, CARD32 *dblend)
+static void i965_get_blend_cntl(int op, PicturePtr pMask, CARD32 dst_format,
+				CARD32 *sblend, CARD32 *dblend)
 {
 
-    *sblend = I965BlendOp[op].src_blend;
-    *dblend = I965BlendOp[op].dst_blend;
+    *sblend = i965_blend_op[op].src_blend;
+    *dblend = i965_blend_op[op].dst_blend;
 
     /* If there's no dst alpha channel, adjust the blend op so that we'll treat
      * it as always 1.
      */
-    if (PICT_FORMAT_A(dst_format) == 0 && I965BlendOp[op].dst_alpha) {
+    if (PICT_FORMAT_A(dst_format) == 0 && i965_blend_op[op].dst_alpha) {
         if (*sblend == BRW_BLENDFACTOR_DST_ALPHA)
             *sblend = BRW_BLENDFACTOR_ONE;
         else if (*sblend == BRW_BLENDFACTOR_INV_DST_ALPHA)
@@ -134,7 +133,7 @@ static void I965GetBlendCntl(int op, PicturePtr pMask, CARD32 dst_format,
      * the source blend factor is 0, and the source blend value is the mask
      * channels multiplied by the source picture's alpha.
      */
-    if (pMask && pMask->componentAlpha && I965BlendOp[op].src_alpha) {
+    if (pMask && pMask->componentAlpha && i965_blend_op[op].src_alpha) {
         if (*dblend == BRW_BLENDFACTOR_SRC_ALPHA) {
 	    *dblend = BRW_BLENDFACTOR_SRC_COLOR;
         } else if (*dblend == BRW_BLENDFACTOR_INV_SRC_ALPHA) {
@@ -144,7 +143,7 @@ static void I965GetBlendCntl(int op, PicturePtr pMask, CARD32 dst_format,
 
 }
 
-static Bool I965GetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format)
+static Bool i965_get_dest_format(PicturePtr pDstPicture, CARD32 *dst_format)
 {
     switch (pDstPicture->format) {
     case PICT_a8r8g8b8:
@@ -172,33 +171,34 @@ static Bool I965GetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format)
     */
     case PICT_a4r4g4b4:
     case PICT_x4r4g4b4:
-	*dst_format = BRW_SURFACEFORMAT_B4G4R4A4_UNORM; 
+	*dst_format = BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
 	break;
     default:
         I830FALLBACK("Unsupported dest format 0x%x\n",
-                        (int)pDstPicture->format);
+		     (int)pDstPicture->format);
     }
 
     return TRUE;
 }
 
-static Bool I965CheckCompositeTexture(PicturePtr pPict, int unit)
+static Bool i965_check_composite_texture(PicturePtr pPict, int unit)
 {
     int w = pPict->pDrawable->width;
     int h = pPict->pDrawable->height;
     int i;
-                                                                                                                                                            
+
     if ((w > 0x7ff) || (h > 0x7ff))
         I830FALLBACK("Picture w/h too large (%dx%d)\n", w, h);
 
-    for (i = 0; i < sizeof(I965TexFormats) / sizeof(I965TexFormats[0]); i++)
+    for (i = 0; i < sizeof(i965_tex_formats) / sizeof(i965_tex_formats[0]);
+	 i++)
     {
-        if (I965TexFormats[i].fmt == pPict->format)
+        if (i965_tex_formats[i].fmt == pPict->format)
             break;
     }
-    if (i == sizeof(I965TexFormats) / sizeof(I965TexFormats[0]))
+    if (i == sizeof(i965_tex_formats) / sizeof(i965_tex_formats[0]))
         I830FALLBACK("Unsupported picture format 0x%x\n",
-                         (int)pPict->format);
+		     (int)pPict->format);
 
     if (pPict->repeat && pPict->repeatType != RepeatNormal)
 	I830FALLBACK("extended repeat (%d) not supported\n",
@@ -206,19 +206,21 @@ static Bool I965CheckCompositeTexture(PicturePtr pPict, int unit)
 
     if (pPict->filter != PictFilterNearest &&
         pPict->filter != PictFilterBilinear)
+    {
         I830FALLBACK("Unsupported filter 0x%x\n", pPict->filter);
+    }
 
     return TRUE;
 }
 
 Bool
-I965EXACheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
-		      PicturePtr pDstPicture)
+i965_check_composite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
+		     PicturePtr pDstPicture)
 {
     CARD32 tmp1;
-    
+
     /* Check for unsupported compositing operations. */
-    if (op >= sizeof(I965BlendOp) / sizeof(I965BlendOp[0]))
+    if (op >= sizeof(i965_blend_op) / sizeof(i965_blend_op[0]))
         I830FALLBACK("Unsupported Composite op 0x%x\n", op);
 
     if (pMaskPicture != NULL && pMaskPicture->componentAlpha) {
@@ -226,20 +228,22 @@ I965EXACheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
          * the source value.  We can only get one of those into the single
          * source value that we get to blend with.
          */
-        if (I965BlendOp[op].src_alpha &&
-            (I965BlendOp[op].src_blend != BRW_BLENDFACTOR_ZERO))
-            	I830FALLBACK("Component alpha not supported with source "
-                            "alpha and source value blending.\n");
+        if (i965_blend_op[op].src_alpha &&
+            (i965_blend_op[op].src_blend != BRW_BLENDFACTOR_ZERO))
+	{
+	    I830FALLBACK("Component alpha not supported with source "
+			 "alpha and source value blending.\n");
+	}
 	/* XXX: fallback now for mask with componentAlpha */
 	I830FALLBACK("mask componentAlpha not ready.\n");
     }
 
-    if (!I965CheckCompositeTexture(pSrcPicture, 0))
+    if (!i965_check_composite_texture(pSrcPicture, 0))
         I830FALLBACK("Check Src picture texture\n");
-    if (pMaskPicture != NULL && !I965CheckCompositeTexture(pMaskPicture, 1))
+    if (pMaskPicture != NULL && !i965_check_composite_texture(pMaskPicture, 1))
         I830FALLBACK("Check Mask picture texture\n");
 
-    if (!I965GetDestFormat(pDstPicture, &tmp1)) 
+    if (!i965_get_dest_format(pDstPicture, &tmp1))
 	I830FALLBACK("Get Color buffer format\n");
 
     return TRUE;
@@ -260,7 +264,7 @@ static struct brw_surface_state *dest_surf_state;
 static struct brw_surface_state *src_surf_state;
 static struct brw_surface_state *mask_surf_state;
 static struct brw_sampler_state *src_sampler_state;
-static struct brw_sampler_state *mask_sampler_state;  
+static struct brw_sampler_state *mask_sampler_state;
 static struct brw_sampler_default_color *default_color_state;
 
 static struct brw_vs_unit_state *vs_state;
@@ -274,7 +278,7 @@ static struct brw_instruction *ps_kernel;
 static struct brw_instruction *sip_kernel;
 
 static CARD32 *binding_table;
-static int binding_table_entries; 
+static int binding_table_entries;
 
 static int dest_surf_offset, src_surf_offset, mask_surf_offset;
 static int src_sampler_offset, mask_sampler_offset,vs_offset;
@@ -282,12 +286,12 @@ static int sf_offset, wm_offset, cc_offset, vb_offset, cc_viewport_offset;
 static int sf_kernel_offset, ps_kernel_offset, sip_kernel_offset;
 static int wm_scratch_offset;
 static int binding_table_offset;
-static int default_color_offset; 
+static int default_color_offset;
 static int next_offset, total_state_size;
 static char *state_base;
 static int state_base_offset;
 static float *vb;
-static int vb_size = (4 * 4) * 4 ; /* 4 DWORDS per vertex*/ 
+static int vb_size = (4 * 4) * 4 ; /* 4 DWORDS per vertex*/
 
 static CARD32 src_blend, dst_blend;
 
@@ -348,20 +352,23 @@ static const CARD32 ps_kernel_static_masknoca [][4] = {
 #include "exa_wm_masknoca_prog.h"
 };
 
-static CARD32 i965_get_card_format(PicturePtr pPict) 
+static CARD32 i965_get_card_format(PicturePtr pPict)
 {
-	int i;
-        for (i = 0; i < sizeof(I965TexFormats) / sizeof(I965TexFormats[0]); i++) {
-            if (I965TexFormats[i].fmt == pPict->format)
-                break;
-        }
-	return I965TexFormats[i].card_fmt;
+    int i;
+
+    for (i = 0; i < sizeof(i965_tex_formats) / sizeof(i965_tex_formats[0]);
+	 i++)
+    {
+	if (i965_tex_formats[i].fmt == pPict->format)
+	    break;
+    }
+    return i965_tex_formats[i].card_fmt;
 }
 
 Bool
-I965EXAPrepareComposite(int op, PicturePtr pSrcPicture,
-			PicturePtr pMaskPicture, PicturePtr pDstPicture,
-			PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst)
+i965_prepare_composite(int op, PicturePtr pSrcPicture,
+		       PicturePtr pMaskPicture, PicturePtr pDstPicture,
+		       PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst)
 {
     ScrnInfoPtr pScrn = xf86Screens[pSrcPicture->pDrawable->pScreen->myNum];
     I830Ptr pI830 = I830PTR(pScrn);
@@ -402,235 +409,241 @@ I965EXAPrepareComposite(int op, PicturePtr pSrcPicture,
 	pI830->scale_units[1][1] = pMask->drawable.height;
     }
 
-	/* setup 3d pipeline state */
-
-   binding_table_entries = 2; /* default no mask */
-
-   /* Wait for sync before we start setting up our new state */
-   i830WaitSync(pScrn);
-
-   /* Set up our layout of state in framebuffer.  First the general state: */
-   next_offset = 0;
-   vs_offset = ALIGN(next_offset, 64);
-   next_offset = vs_offset + sizeof(*vs_state);
-    
-   sf_offset = ALIGN(next_offset, 32);
-   next_offset = sf_offset + sizeof(*sf_state);
-    
-   wm_offset = ALIGN(next_offset, 32);
-   next_offset = wm_offset + sizeof(*wm_state);
-    
-   wm_scratch_offset = ALIGN(next_offset, 1024);
-   next_offset = wm_scratch_offset + 1024 * PS_MAX_THREADS;
-
-   cc_offset = ALIGN(next_offset, 32);
-   next_offset = cc_offset + sizeof(*cc_state);
-
-   /* keep current sf_kernel, which will send one setup urb entry to
-	PS kernel */
-   sf_kernel_offset = ALIGN(next_offset, 64);
-   if (pMask) 
-       next_offset = sf_kernel_offset + sizeof (sf_kernel_static_mask);
-   else
-       next_offset = sf_kernel_offset + sizeof (sf_kernel_static);
-
-   //XXX: ps_kernel may be seperated, fix with offset
-   ps_kernel_offset = ALIGN(next_offset, 64);
-   if (pMask) {
+    /* setup 3d pipeline state */
+
+    binding_table_entries = 2; /* default no mask */
+
+    /* Wait for sync before we start setting up our new state */
+    i830WaitSync(pScrn);
+
+    /* Set up our layout of state in framebuffer.  First the general state: */
+    next_offset = 0;
+    vs_offset = ALIGN(next_offset, 64);
+    next_offset = vs_offset + sizeof(*vs_state);
+
+    sf_offset = ALIGN(next_offset, 32);
+    next_offset = sf_offset + sizeof(*sf_state);
+
+    wm_offset = ALIGN(next_offset, 32);
+    next_offset = wm_offset + sizeof(*wm_state);
+
+    wm_scratch_offset = ALIGN(next_offset, 1024);
+    next_offset = wm_scratch_offset + 1024 * PS_MAX_THREADS;
+
+    cc_offset = ALIGN(next_offset, 32);
+    next_offset = cc_offset + sizeof(*cc_state);
+
+    /* keep current sf_kernel, which will send one setup urb entry to
+     * PS kernel
+     */
+    sf_kernel_offset = ALIGN(next_offset, 64);
+    if (pMask)
+	next_offset = sf_kernel_offset + sizeof (sf_kernel_static_mask);
+    else
+	next_offset = sf_kernel_offset + sizeof (sf_kernel_static);
+
+    /* XXX: ps_kernel may be seperated, fix with offset */
+    ps_kernel_offset = ALIGN(next_offset, 64);
+    if (pMask) {
 	if (pMaskPicture->componentAlpha)
 	    next_offset = ps_kernel_offset + sizeof(ps_kernel_static_maskca);
-	else 
+	else
 	    next_offset = ps_kernel_offset + sizeof(ps_kernel_static_masknoca);
-   } else 
+    } else {
    	next_offset = ps_kernel_offset + sizeof (ps_kernel_static_nomask);
-    
-   sip_kernel_offset = ALIGN(next_offset, 64);
-   next_offset = sip_kernel_offset + sizeof (sip_kernel_static);
-   
-   // needed?
-   cc_viewport_offset = ALIGN(next_offset, 32);
-   next_offset = cc_viewport_offset + sizeof(*cc_viewport);
-
-   // for texture sampler
-   src_sampler_offset = ALIGN(next_offset, 32);
-   next_offset = src_sampler_offset + sizeof(*src_sampler_state);
-
-   if (pMask) {
+    }
+
+    sip_kernel_offset = ALIGN(next_offset, 64);
+    next_offset = sip_kernel_offset + sizeof (sip_kernel_static);
+
+    /* needed? */
+    cc_viewport_offset = ALIGN(next_offset, 32);
+    next_offset = cc_viewport_offset + sizeof(*cc_viewport);
+
+    /* for texture sampler */
+    src_sampler_offset = ALIGN(next_offset, 32);
+    next_offset = src_sampler_offset + sizeof(*src_sampler_state);
+
+    if (pMask) {
    	mask_sampler_offset = ALIGN(next_offset, 32);
    	next_offset = mask_sampler_offset + sizeof(*mask_sampler_state);
-   }
-   /* Align VB to native size of elements, for safety */
-   vb_offset = ALIGN(next_offset, 8);
-   next_offset = vb_offset + vb_size;
+    }
+    /* Align VB to native size of elements, for safety */
+    vb_offset = ALIGN(next_offset, 8);
+    next_offset = vb_offset + vb_size;
 
-   /* And then the general state: */
-   dest_surf_offset = ALIGN(next_offset, 32);
-   next_offset = dest_surf_offset + sizeof(*dest_surf_state);
+    /* And then the general state: */
+    dest_surf_offset = ALIGN(next_offset, 32);
+    next_offset = dest_surf_offset + sizeof(*dest_surf_state);
 
-   src_surf_offset = ALIGN(next_offset, 32);
-   next_offset = src_surf_offset + sizeof(*src_surf_state);
+    src_surf_offset = ALIGN(next_offset, 32);
+    next_offset = src_surf_offset + sizeof(*src_surf_state);
 
-   if (pMask) {
+    if (pMask) {
    	mask_surf_offset = ALIGN(next_offset, 32);
    	next_offset = mask_surf_offset + sizeof(*mask_surf_state);
 	binding_table_entries = 3;
-   }
-
-   binding_table_offset = ALIGN(next_offset, 32);
-   next_offset = binding_table_offset + (binding_table_entries * 4);
-
-   default_color_offset = ALIGN(next_offset, 32);
-   next_offset = default_color_offset + sizeof(*default_color_state);
-
-   total_state_size = next_offset;
-   assert(total_state_size < EXA_LINEAR_EXTRA);
-
-   state_base_offset = pI830->EXAStateMem.Start;
-   state_base_offset = ALIGN(state_base_offset, 64);
-   state_base = (char *)(pI830->FbBase + state_base_offset);
-
-   vs_state = (void *)(state_base + vs_offset);
-   sf_state = (void *)(state_base + sf_offset);
-   wm_state = (void *)(state_base + wm_offset);
-   cc_state = (void *)(state_base + cc_offset);
-   sf_kernel = (void *)(state_base + sf_kernel_offset);
-   ps_kernel = (void *)(state_base + ps_kernel_offset);
-   sip_kernel = (void *)(state_base + sip_kernel_offset);
-   
-   cc_viewport = (void *)(state_base + cc_viewport_offset);
-   
-   dest_surf_state = (void *)(state_base + dest_surf_offset);
-   src_surf_state = (void *)(state_base + src_surf_offset);
-   if (pMask)
+    }
+
+    binding_table_offset = ALIGN(next_offset, 32);
+    next_offset = binding_table_offset + (binding_table_entries * 4);
+
+    default_color_offset = ALIGN(next_offset, 32);
+    next_offset = default_color_offset + sizeof(*default_color_state);
+
+    total_state_size = next_offset;
+    assert(total_state_size < EXA_LINEAR_EXTRA);
+
+    state_base_offset = pI830->EXAStateMem.Start;
+    state_base_offset = ALIGN(state_base_offset, 64);
+    state_base = (char *)(pI830->FbBase + state_base_offset);
+
+    vs_state = (void *)(state_base + vs_offset);
+    sf_state = (void *)(state_base + sf_offset);
+    wm_state = (void *)(state_base + wm_offset);
+    cc_state = (void *)(state_base + cc_offset);
+    sf_kernel = (void *)(state_base + sf_kernel_offset);
+    ps_kernel = (void *)(state_base + ps_kernel_offset);
+    sip_kernel = (void *)(state_base + sip_kernel_offset);
+
+    cc_viewport = (void *)(state_base + cc_viewport_offset);
+
+    dest_surf_state = (void *)(state_base + dest_surf_offset);
+    src_surf_state = (void *)(state_base + src_surf_offset);
+    if (pMask)
 	mask_surf_state = (void *)(state_base + mask_surf_offset);
 
-   src_sampler_state = (void *)(state_base + src_sampler_offset);
-   if (pMask)
+    src_sampler_state = (void *)(state_base + src_sampler_offset);
+    if (pMask)
 	mask_sampler_state = (void *)(state_base + mask_sampler_offset);
 
-   binding_table = (void *)(state_base + binding_table_offset);
+    binding_table = (void *)(state_base + binding_table_offset);
 
-   vb = (void *)(state_base + vb_offset);
+    vb = (void *)(state_base + vb_offset);
 
-   default_color_state = (void*)(state_base + default_color_offset);
+    default_color_state = (void*)(state_base + default_color_offset);
 
-   /* Set up a default static partitioning of the URB, which is supposed to
-    * allow anything we would want to do, at potentially lower performance.
-    */
+    /* Set up a default static partitioning of the URB, which is supposed to
+     * allow anything we would want to do, at potentially lower performance.
+     */
 #define URB_CS_ENTRY_SIZE     0
 #define URB_CS_ENTRIES	      0
-   
+
 #define URB_VS_ENTRY_SIZE     1	  // each 512-bit row
 #define URB_VS_ENTRIES	      8	  // we needs at least 8 entries
-   
+
 #define URB_GS_ENTRY_SIZE     0
 #define URB_GS_ENTRIES	      0
-   
+
 #define URB_CLIP_ENTRY_SIZE   0
 #define URB_CLIP_ENTRIES      0
-   
+
 #define URB_SF_ENTRY_SIZE     2
 #define URB_SF_ENTRIES	      1
 
-   urb_vs_start = 0;
-   urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE;
-   urb_gs_start = urb_vs_start + urb_vs_size;
-   urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE;
-   urb_clip_start = urb_gs_start + urb_gs_size;
-   urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE;
-   urb_sf_start = urb_clip_start + urb_clip_size;
-   urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE;
-   urb_cs_start = urb_sf_start + urb_sf_size;
-   urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE;
-
-   /* We'll be poking the state buffers that could be in use by the 3d hardware
-    * here, but we should have synced the 3D engine already in I830PutImage.
-    */
+    urb_vs_start = 0;
+    urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE;
+    urb_gs_start = urb_vs_start + urb_vs_size;
+    urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE;
+    urb_clip_start = urb_gs_start + urb_gs_size;
+    urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE;
+    urb_sf_start = urb_clip_start + urb_clip_size;
+    urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE;
+    urb_cs_start = urb_sf_start + urb_sf_size;
+    urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE;
+
+    /* We'll be poking the state buffers that could be in use by the 3d
+     * hardware here, but we should have synced the 3D engine already in
+     * I830PutImage. XXX
+     */
 
-   memset (cc_viewport, 0, sizeof (*cc_viewport));
-   cc_viewport->min_depth = -1.e35;
-   cc_viewport->max_depth = 1.e35;
-
-   /* Color calculator state */
-   memset(cc_state, 0, sizeof(*cc_state));
-   cc_state->cc0.stencil_enable = 0;   /* disable stencil */
-   cc_state->cc2.depth_test = 0;       /* disable depth test */
-   cc_state->cc2.logicop_enable = 0;   /* disable logic op */
-   cc_state->cc3.ia_blend_enable = 1;  /* blend alpha just like colors */
-   cc_state->cc3.blend_enable = 1;     /* enable color blend */
-   cc_state->cc3.alpha_test = 0;       /* disable alpha test */
-   cc_state->cc4.cc_viewport_state_offset = (state_base_offset + cc_viewport_offset) >> 5;
-   cc_state->cc5.dither_enable = 0;    /* disable dither */
-   cc_state->cc5.logicop_func = 0xc;   /* COPY */
-   cc_state->cc5.statistics_enable = 1;
-   cc_state->cc5.ia_blend_function = BRW_BLENDFUNCTION_ADD;
-   I965GetBlendCntl(op, pMaskPicture, pDstPicture->format, 
-		    &src_blend, &dst_blend);
-   /* XXX: alpha blend factor should be same as color, but check
-	   for CA case in future */
-   cc_state->cc5.ia_src_blend_factor = src_blend;
-   cc_state->cc5.ia_dest_blend_factor = dst_blend;
-   cc_state->cc6.blend_function = BRW_BLENDFUNCTION_ADD;
-   cc_state->cc6.src_blend_factor = src_blend;
-   cc_state->cc6.dest_blend_factor = dst_blend;
-   cc_state->cc6.clamp_post_alpha_blend = 1; 
-   cc_state->cc6.clamp_pre_alpha_blend = 1; 
-   cc_state->cc6.clamp_range = 0;  /* clamp range [0,1] */
-
-   /* Upload system kernel */
-   memcpy (sip_kernel, sip_kernel_static, sizeof (sip_kernel_static));
-   
-   /* Set up the state buffer for the destination surface */
-   memset(dest_surf_state, 0, sizeof(*dest_surf_state));
-   dest_surf_state->ss0.surface_type = BRW_SURFACE_2D;
-   dest_surf_state->ss0.data_return_format = BRW_SURFACERETURNFORMAT_FLOAT32;
-   I965GetDestFormat(pDstPicture, &dst_format);
-   dest_surf_state->ss0.surface_format = dst_format;
-
-   dest_surf_state->ss0.writedisable_alpha = 0;
-   dest_surf_state->ss0.writedisable_red = 0;
-   dest_surf_state->ss0.writedisable_green = 0;
-   dest_surf_state->ss0.writedisable_blue = 0;
-   dest_surf_state->ss0.color_blend = 1;
-   dest_surf_state->ss0.vert_line_stride = 0;
-   dest_surf_state->ss0.vert_line_stride_ofs = 0;
-   dest_surf_state->ss0.mipmap_layout_mode = 0;
-   dest_surf_state->ss0.render_cache_read_mode = 0;
-   
-   dest_surf_state->ss1.base_addr = dst_offset;
-   dest_surf_state->ss2.height = pDst->drawable.height - 1;
-   dest_surf_state->ss2.width = pDst->drawable.width - 1;
-   dest_surf_state->ss2.mip_count = 0;
-   dest_surf_state->ss2.render_target_rotation = 0;
-   dest_surf_state->ss3.pitch = dst_pitch - 1; 
-
-   /* Set up the source surface state buffer */
-   memset(src_surf_state, 0, sizeof(*src_surf_state));
-   src_surf_state->ss0.surface_type = BRW_SURFACE_2D;
-   src_surf_state->ss0.surface_format = i965_get_card_format(pSrcPicture);
-
-   src_surf_state->ss0.writedisable_alpha = 0;
-   src_surf_state->ss0.writedisable_red = 0;
-   src_surf_state->ss0.writedisable_green = 0;
-   src_surf_state->ss0.writedisable_blue = 0;
-   src_surf_state->ss0.color_blend = 1;
-   src_surf_state->ss0.vert_line_stride = 0;
-   src_surf_state->ss0.vert_line_stride_ofs = 0;
-   src_surf_state->ss0.mipmap_layout_mode = 0;
-   src_surf_state->ss0.render_cache_read_mode = 0;
-   
-   src_surf_state->ss1.base_addr = src_offset;
-   src_surf_state->ss2.width = pSrc->drawable.width - 1;
-   src_surf_state->ss2.height = pSrc->drawable.height - 1;
-   src_surf_state->ss2.mip_count = 0;
-   src_surf_state->ss2.render_target_rotation = 0;
-   src_surf_state->ss3.pitch = src_pitch - 1; 
-
-   /* setup mask surface */
-   if (pMask) {
+    memset (cc_viewport, 0, sizeof (*cc_viewport));
+    cc_viewport->min_depth = -1.e35;
+    cc_viewport->max_depth = 1.e35;
+
+    /* Color calculator state */
+    memset(cc_state, 0, sizeof(*cc_state));
+    cc_state->cc0.stencil_enable = 0;   /* disable stencil */
+    cc_state->cc2.depth_test = 0;       /* disable depth test */
+    cc_state->cc2.logicop_enable = 0;   /* disable logic op */
+    cc_state->cc3.ia_blend_enable = 1;  /* blend alpha just like colors */
+    cc_state->cc3.blend_enable = 1;     /* enable color blend */
+    cc_state->cc3.alpha_test = 0;       /* disable alpha test */
+    cc_state->cc4.cc_viewport_state_offset = (state_base_offset +
+					      cc_viewport_offset) >> 5;
+    cc_state->cc5.dither_enable = 0;    /* disable dither */
+    cc_state->cc5.logicop_func = 0xc;   /* COPY */
+    cc_state->cc5.statistics_enable = 1;
+    cc_state->cc5.ia_blend_function = BRW_BLENDFUNCTION_ADD;
+    i965_get_blend_cntl(op, pMaskPicture, pDstPicture->format,
+			&src_blend, &dst_blend);
+    /* XXX: alpha blend factor should be same as color, but check
+     * for CA case in future
+     */
+    cc_state->cc5.ia_src_blend_factor = src_blend;
+    cc_state->cc5.ia_dest_blend_factor = dst_blend;
+    cc_state->cc6.blend_function = BRW_BLENDFUNCTION_ADD;
+    cc_state->cc6.src_blend_factor = src_blend;
+    cc_state->cc6.dest_blend_factor = dst_blend;
+    cc_state->cc6.clamp_post_alpha_blend = 1;
+    cc_state->cc6.clamp_pre_alpha_blend = 1;
+    cc_state->cc6.clamp_range = 0;  /* clamp range [0,1] */
+
+    /* Upload system kernel */
+    memcpy (sip_kernel, sip_kernel_static, sizeof (sip_kernel_static));
+
+    /* Set up the state buffer for the destination surface */
+    memset(dest_surf_state, 0, sizeof(*dest_surf_state));
+    dest_surf_state->ss0.surface_type = BRW_SURFACE_2D;
+    dest_surf_state->ss0.data_return_format = BRW_SURFACERETURNFORMAT_FLOAT32;
+    i965_get_dest_format(pDstPicture, &dst_format);
+    dest_surf_state->ss0.surface_format = dst_format;
+
+    dest_surf_state->ss0.writedisable_alpha = 0;
+    dest_surf_state->ss0.writedisable_red = 0;
+    dest_surf_state->ss0.writedisable_green = 0;
+    dest_surf_state->ss0.writedisable_blue = 0;
+    dest_surf_state->ss0.color_blend = 1;
+    dest_surf_state->ss0.vert_line_stride = 0;
+    dest_surf_state->ss0.vert_line_stride_ofs = 0;
+    dest_surf_state->ss0.mipmap_layout_mode = 0;
+    dest_surf_state->ss0.render_cache_read_mode = 0;
+
+    dest_surf_state->ss1.base_addr = dst_offset;
+    dest_surf_state->ss2.height = pDst->drawable.height - 1;
+    dest_surf_state->ss2.width = pDst->drawable.width - 1;
+    dest_surf_state->ss2.mip_count = 0;
+    dest_surf_state->ss2.render_target_rotation = 0;
+    dest_surf_state->ss3.pitch = dst_pitch - 1;
+
+    /* Set up the source surface state buffer */
+    memset(src_surf_state, 0, sizeof(*src_surf_state));
+    src_surf_state->ss0.surface_type = BRW_SURFACE_2D;
+    src_surf_state->ss0.surface_format = i965_get_card_format(pSrcPicture);
+
+    src_surf_state->ss0.writedisable_alpha = 0;
+    src_surf_state->ss0.writedisable_red = 0;
+    src_surf_state->ss0.writedisable_green = 0;
+    src_surf_state->ss0.writedisable_blue = 0;
+    src_surf_state->ss0.color_blend = 1;
+    src_surf_state->ss0.vert_line_stride = 0;
+    src_surf_state->ss0.vert_line_stride_ofs = 0;
+    src_surf_state->ss0.mipmap_layout_mode = 0;
+    src_surf_state->ss0.render_cache_read_mode = 0;
+
+    src_surf_state->ss1.base_addr = src_offset;
+    src_surf_state->ss2.width = pSrc->drawable.width - 1;
+    src_surf_state->ss2.height = pSrc->drawable.height - 1;
+    src_surf_state->ss2.mip_count = 0;
+    src_surf_state->ss2.render_target_rotation = 0;
+    src_surf_state->ss3.pitch = src_pitch - 1;
+
+    /* setup mask surface */
+    if (pMask) {
    	memset(mask_surf_state, 0, sizeof(*mask_surf_state));
 	mask_surf_state->ss0.surface_type = BRW_SURFACE_2D;
-   	mask_surf_state->ss0.surface_format = i965_get_card_format(pMaskPicture);
+   	mask_surf_state->ss0.surface_format =
+	    i965_get_card_format(pMaskPicture);
 
    	mask_surf_state->ss0.writedisable_alpha = 0;
    	mask_surf_state->ss0.writedisable_red = 0;
@@ -641,68 +654,68 @@ I965EXAPrepareComposite(int op, PicturePtr pSrcPicture,
    	mask_surf_state->ss0.vert_line_stride_ofs = 0;
    	mask_surf_state->ss0.mipmap_layout_mode = 0;
    	mask_surf_state->ss0.render_cache_read_mode = 0;
-   
+
    	mask_surf_state->ss1.base_addr = mask_offset;
    	mask_surf_state->ss2.width = pMask->drawable.width - 1;
    	mask_surf_state->ss2.height = pMask->drawable.height - 1;
    	mask_surf_state->ss2.mip_count = 0;
    	mask_surf_state->ss2.render_target_rotation = 0;
-   	mask_surf_state->ss3.pitch = mask_pitch - 1; 
-   }
+   	mask_surf_state->ss3.pitch = mask_pitch - 1;
+    }
 
-   /* Set up a binding table for our surfaces.  Only the PS will use it */
-   binding_table[0] = state_base_offset + dest_surf_offset;
-   binding_table[1] = state_base_offset + src_surf_offset;
-   if (pMask)
+    /* Set up a binding table for our surfaces.  Only the PS will use it */
+    binding_table[0] = state_base_offset + dest_surf_offset;
+    binding_table[1] = state_base_offset + src_surf_offset;
+    if (pMask)
    	binding_table[2] = state_base_offset + mask_surf_offset;
 
-   /* PS kernel use this sampler */
-   memset(src_sampler_state, 0, sizeof(*src_sampler_state));
-   src_sampler_state->ss0.lod_preclamp = 1; /* GL mode */
-   switch(pSrcPicture->filter) {
-   case PictFilterNearest:
-   	src_sampler_state->ss0.min_filter = BRW_MAPFILTER_NEAREST; 
+    /* PS kernel use this sampler */
+    memset(src_sampler_state, 0, sizeof(*src_sampler_state));
+    src_sampler_state->ss0.lod_preclamp = 1; /* GL mode */
+    switch(pSrcPicture->filter) {
+    case PictFilterNearest:
+   	src_sampler_state->ss0.min_filter = BRW_MAPFILTER_NEAREST;
    	src_sampler_state->ss0.mag_filter = BRW_MAPFILTER_NEAREST;
 	break;
-   case PictFilterBilinear:
-   	src_sampler_state->ss0.min_filter = BRW_MAPFILTER_LINEAR; 
+    case PictFilterBilinear:
+	src_sampler_state->ss0.min_filter = BRW_MAPFILTER_LINEAR;
    	src_sampler_state->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
 	break;
-   default:
+    default:
 	I830FALLBACK("Bad filter 0x%x\n", pSrcPicture->filter);
-   }
+    }
 
-   memset(default_color_state, 0, sizeof(*default_color_state));
-   default_color_state->color[0] = 0.0; /* R */
-   default_color_state->color[1] = 0.0; /* G */
-   default_color_state->color[2] = 0.0; /* B */
-   default_color_state->color[3] = 1.0; /* A */
+    memset(default_color_state, 0, sizeof(*default_color_state));
+    default_color_state->color[0] = 0.0; /* R */
+    default_color_state->color[1] = 0.0; /* G */
+    default_color_state->color[2] = 0.0; /* B */
+    default_color_state->color[3] = 1.0; /* A */
 
-   src_sampler_state->ss0.default_color_mode = 0; /* GL mode */
+    src_sampler_state->ss0.default_color_mode = 0; /* GL mode */
 
-   if (!pSrcPicture->repeat) {
-   	src_sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER; 
+    if (!pSrcPicture->repeat) {
+   	src_sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER;
    	src_sampler_state->ss1.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER;
    	src_sampler_state->ss1.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER;
-	src_sampler_state->ss2.default_color_pointer = 
-			(state_base_offset + default_color_offset) >> 5;
-   } else {
-   	src_sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_WRAP; 
+	src_sampler_state->ss2.default_color_pointer =
+	    (state_base_offset + default_color_offset) >> 5;
+    } else {
+   	src_sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_WRAP;
    	src_sampler_state->ss1.s_wrap_mode = BRW_TEXCOORDMODE_WRAP;
    	src_sampler_state->ss1.t_wrap_mode = BRW_TEXCOORDMODE_WRAP;
-   }
-   src_sampler_state->ss3.chroma_key_enable = 0; /* disable chromakey */
+    }
+    src_sampler_state->ss3.chroma_key_enable = 0; /* disable chromakey */
 
-   if (pMask) {
+    if (pMask) {
    	memset(mask_sampler_state, 0, sizeof(*mask_sampler_state));
    	mask_sampler_state->ss0.lod_preclamp = 1; /* GL mode */
    	switch(pMaskPicture->filter) {
    	case PictFilterNearest:
-   	    mask_sampler_state->ss0.min_filter = BRW_MAPFILTER_NEAREST; 
+   	    mask_sampler_state->ss0.min_filter = BRW_MAPFILTER_NEAREST;
    	    mask_sampler_state->ss0.mag_filter = BRW_MAPFILTER_NEAREST;
 	    break;
    	case PictFilterBilinear:
-   	    mask_sampler_state->ss0.min_filter = BRW_MAPFILTER_LINEAR; 
+   	    mask_sampler_state->ss0.min_filter = BRW_MAPFILTER_LINEAR;
    	    mask_sampler_state->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
 	    break;
    	default:
@@ -710,189 +723,203 @@ I965EXAPrepareComposite(int op, PicturePtr pSrcPicture,
    	}
 
    	if (!pMaskPicture->repeat) {
-   	    mask_sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER; 
-   	    mask_sampler_state->ss1.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER;
-   	    mask_sampler_state->ss1.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER;
-            mask_sampler_state->ss2.default_color_pointer = 
-				(state_base_offset + default_color_offset)>>5;
+   	    mask_sampler_state->ss1.r_wrap_mode =
+		BRW_TEXCOORDMODE_CLAMP_BORDER;
+   	    mask_sampler_state->ss1.s_wrap_mode =
+		BRW_TEXCOORDMODE_CLAMP_BORDER;
+   	    mask_sampler_state->ss1.t_wrap_mode =
+		BRW_TEXCOORDMODE_CLAMP_BORDER;
+            mask_sampler_state->ss2.default_color_pointer =
+		(state_base_offset + default_color_offset)>>5;
    	} else {
-   	    mask_sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_WRAP; 
+   	    mask_sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_WRAP;
    	    mask_sampler_state->ss1.s_wrap_mode = BRW_TEXCOORDMODE_WRAP;
    	    mask_sampler_state->ss1.t_wrap_mode = BRW_TEXCOORDMODE_WRAP;
     	}
    	mask_sampler_state->ss3.chroma_key_enable = 0; /* disable chromakey */
-   }
-
-   /* Set up the vertex shader to be disabled (passthrough) */
-   memset(vs_state, 0, sizeof(*vs_state));
-   vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
-   vs_state->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
-   vs_state->vs6.vs_enable = 0;
-   vs_state->vs6.vert_cache_disable = 1;
-
-   // XXX: sf_kernel? keep it as now
-   /* Set up the SF kernel to do coord interp: for each attribute,
-    * calculate dA/dx and dA/dy.  Hand these interpolation coefficients
-    * back to SF which then hands pixels off to WM.
-    */
-   if (pMask) 
-       memcpy (sf_kernel, sf_kernel_static_mask, sizeof (sf_kernel_static));
-   else
-       memcpy (sf_kernel, sf_kernel_static, sizeof (sf_kernel_static));
-
-   memset(sf_state, 0, sizeof(*sf_state));
-   sf_state->thread0.kernel_start_pointer = 
-	       (state_base_offset + sf_kernel_offset) >> 6;
-   sf_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
-   sf_state->sf1.single_program_flow = 1;
-   sf_state->sf1.binding_table_entry_count = 0;
-   sf_state->sf1.thread_priority = 0;
-   sf_state->sf1.floating_point_mode = 0; /* Mesa does this */
-   sf_state->sf1.illegal_op_exception_enable = 1;
-   sf_state->sf1.mask_stack_exception_enable = 1;
-   sf_state->sf1.sw_exception_enable = 1;
-   sf_state->thread2.per_thread_scratch_space = 0;
-   sf_state->thread2.scratch_space_base_pointer = 0; /* not used in our kernel */
-   sf_state->thread3.const_urb_entry_read_length = 0; /* no const URBs */
-   sf_state->thread3.const_urb_entry_read_offset = 0; /* no const URBs */
-   sf_state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */
-   sf_state->thread3.urb_entry_read_offset = 0;
-   sf_state->thread3.dispatch_grf_start_reg = 3;
-   sf_state->thread4.max_threads = SF_MAX_THREADS - 1;
-   sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
-   sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES;
-   sf_state->thread4.stats_enable = 1;
-   sf_state->sf5.viewport_transform = FALSE; /* skip viewport */
-   sf_state->sf6.cull_mode = BRW_CULLMODE_NONE;
-   sf_state->sf6.scissor = 0;
-   sf_state->sf7.trifan_pv = 2;
-   sf_state->sf6.dest_org_vbias = 0x8;
-   sf_state->sf6.dest_org_hbias = 0x8;
-
-   /* Set up the PS kernel (dispatched by WM) 
-    */
-    
-   if (pMask) {
+    }
+
+    /* Set up the vertex shader to be disabled (passthrough) */
+    memset(vs_state, 0, sizeof(*vs_state));
+    vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
+    vs_state->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
+    vs_state->vs6.vs_enable = 0;
+    vs_state->vs6.vert_cache_disable = 1;
+
+    /* XXX: sf_kernel? keep it as now */
+    /* Set up the SF kernel to do coord interp: for each attribute,
+     * calculate dA/dx and dA/dy.  Hand these interpolation coefficients
+     * back to SF which then hands pixels off to WM.
+     */
+    if (pMask)
+	memcpy(sf_kernel, sf_kernel_static_mask, sizeof (sf_kernel_static));
+    else
+	memcpy(sf_kernel, sf_kernel_static, sizeof (sf_kernel_static));
+
+    memset(sf_state, 0, sizeof(*sf_state));
+    sf_state->thread0.kernel_start_pointer =
+	(state_base_offset + sf_kernel_offset) >> 6;
+    sf_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
+    sf_state->sf1.single_program_flow = 1;
+    sf_state->sf1.binding_table_entry_count = 0;
+    sf_state->sf1.thread_priority = 0;
+    sf_state->sf1.floating_point_mode = 0; /* Mesa does this */
+    sf_state->sf1.illegal_op_exception_enable = 1;
+    sf_state->sf1.mask_stack_exception_enable = 1;
+    sf_state->sf1.sw_exception_enable = 1;
+    sf_state->thread2.per_thread_scratch_space = 0;
+    /* scratch space is not used in our kernel */
+    sf_state->thread2.scratch_space_base_pointer = 0;
+    sf_state->thread3.const_urb_entry_read_length = 0; /* no const URBs */
+    sf_state->thread3.const_urb_entry_read_offset = 0; /* no const URBs */
+    sf_state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */
+    sf_state->thread3.urb_entry_read_offset = 0;
+    sf_state->thread3.dispatch_grf_start_reg = 3;
+    sf_state->thread4.max_threads = SF_MAX_THREADS - 1;
+    sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
+    sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES;
+    sf_state->thread4.stats_enable = 1;
+    sf_state->sf5.viewport_transform = FALSE; /* skip viewport */
+    sf_state->sf6.cull_mode = BRW_CULLMODE_NONE;
+    sf_state->sf6.scissor = 0;
+    sf_state->sf7.trifan_pv = 2;
+    sf_state->sf6.dest_org_vbias = 0x8;
+    sf_state->sf6.dest_org_hbias = 0x8;
+
+   /* Set up the PS kernel (dispatched by WM) */
+    if (pMask) {
 	if (pMaskPicture->componentAlpha)
-   	    memcpy (ps_kernel, ps_kernel_static_maskca, sizeof (ps_kernel_static_maskca));
+   	    memcpy(ps_kernel, ps_kernel_static_maskca,
+		   sizeof (ps_kernel_static_maskca));
 	else
-   	    memcpy (ps_kernel, ps_kernel_static_masknoca, sizeof (ps_kernel_static_masknoca));
-   } else 
-   	memcpy (ps_kernel, ps_kernel_static_nomask, sizeof (ps_kernel_static_nomask));
-
-   memset (wm_state, 0, sizeof (*wm_state));
-   wm_state->thread0.kernel_start_pointer = 
-	    (state_base_offset + ps_kernel_offset) >> 6;
-   wm_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
-   wm_state->thread1.single_program_flow = 1;
-   if (!pMask)
-       wm_state->thread1.binding_table_entry_count = 2; /* 1 tex and fb */
-   else
-       wm_state->thread1.binding_table_entry_count = 3; /* 2 tex and fb */
-
-   wm_state->thread2.scratch_space_base_pointer = (state_base_offset + 
-						   wm_scratch_offset)>>10;
-   wm_state->thread2.per_thread_scratch_space = 0;
-   // XXX: urb allocation
-   wm_state->thread3.const_urb_entry_read_length = 0;
-   wm_state->thread3.const_urb_entry_read_offset = 0;
-   if (pMask)
-       wm_state->thread3.urb_entry_read_length = 2;  /* two per pair of attrib */
-   else 
-       wm_state->thread3.urb_entry_read_length = 1;  /* one per pair of attrib */
-   wm_state->thread3.urb_entry_read_offset = 0;
-   // wm kernel use urb from 3, see wm_program in compiler module
-   wm_state->thread3.dispatch_grf_start_reg = 3; /* must match kernel */
-
-   wm_state->wm4.stats_enable = 1;  /* statistic */
-   wm_state->wm4.sampler_state_pointer = (state_base_offset + src_sampler_offset) >> 5; 
-   wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
-   wm_state->wm5.max_threads = PS_MAX_THREADS - 1;
-   wm_state->wm5.thread_dispatch_enable = 1;
-   //just use 16-pixel dispatch (4 subspans), don't need to change kernel start point
-   wm_state->wm5.enable_16_pix = 1;
-   wm_state->wm5.enable_8_pix = 0;
-   wm_state->wm5.early_depth_test = 1;
-
-   /* Begin the long sequence of commands needed to set up the 3D 
-    * rendering pipe
-    */
-   {
+   	    memcpy(ps_kernel, ps_kernel_static_masknoca,
+		   sizeof (ps_kernel_static_masknoca));
+    } else {
+   	memcpy(ps_kernel, ps_kernel_static_nomask,
+	       sizeof (ps_kernel_static_nomask));
+    }
+
+    memset(wm_state, 0, sizeof (*wm_state));
+    wm_state->thread0.kernel_start_pointer =
+	(state_base_offset + ps_kernel_offset) >> 6;
+    wm_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
+    wm_state->thread1.single_program_flow = 1;
+    if (!pMask)
+	wm_state->thread1.binding_table_entry_count = 2; /* 1 tex and fb */
+    else
+	wm_state->thread1.binding_table_entry_count = 3; /* 2 tex and fb */
+
+    wm_state->thread2.scratch_space_base_pointer = (state_base_offset +
+						    wm_scratch_offset)>>10;
+    wm_state->thread2.per_thread_scratch_space = 0;
+    // XXX: urb allocation
+    wm_state->thread3.const_urb_entry_read_length = 0;
+    wm_state->thread3.const_urb_entry_read_offset = 0;
+    /* Each pair of attributes (src/mask coords) is one URB entry */
+    if (pMask)
+	wm_state->thread3.urb_entry_read_length = 2;
+    else
+	wm_state->thread3.urb_entry_read_length = 1;
+    wm_state->thread3.urb_entry_read_offset = 0;
+    /* wm kernel use urb from 3, see wm_program in compiler module */
+    wm_state->thread3.dispatch_grf_start_reg = 3; /* must match kernel */
+
+    wm_state->wm4.stats_enable = 1;  /* statistic */
+    wm_state->wm4.sampler_state_pointer = (state_base_offset +
+					   src_sampler_offset) >> 5;
+    wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
+    wm_state->wm5.max_threads = PS_MAX_THREADS - 1;
+    wm_state->wm5.thread_dispatch_enable = 1;
+    /* just use 16-pixel dispatch (4 subspans), don't need to change kernel
+     * start point
+     */
+    wm_state->wm5.enable_16_pix = 1;
+    wm_state->wm5.enable_8_pix = 0;
+    wm_state->wm5.early_depth_test = 1;
+
+    /* Begin the long sequence of commands needed to set up the 3D
+     * rendering pipe
+     */
+    {
 	BEGIN_LP_RING(2);
-   	OUT_RING(MI_FLUSH | 
-	    MI_STATE_INSTRUCTION_CACHE_FLUSH |
-	    BRW_MI_GLOBAL_SNAPSHOT_RESET);
+   	OUT_RING(MI_FLUSH |
+		 MI_STATE_INSTRUCTION_CACHE_FLUSH |
+		 BRW_MI_GLOBAL_SNAPSHOT_RESET);
 	OUT_RING(MI_NOOP);
 	ADVANCE_LP_RING();
-   }
-   {
+    }
+    {
         BEGIN_LP_RING(12);
-   
+
         /* Match Mesa driver setup */
         OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
-   
+
    	OUT_RING(BRW_CS_URB_STATE | 0);
    	OUT_RING((0 << 4) |  /* URB Entry Allocation Size */
-            (0 << 0));  /* Number of URB Entries */
+		 (0 << 0));  /* Number of URB Entries */
 
-   /* Zero out the two base address registers so all offsets are absolute */
+	/* Zero out the two base address registers so all offsets are
+	 * absolute.
+	 */
    	OUT_RING(BRW_STATE_BASE_ADDRESS | 4);
    	OUT_RING(0 | BASE_ADDRESS_MODIFY);  /* Generate state base address */
    	OUT_RING(0 | BASE_ADDRESS_MODIFY);  /* Surface state base address */
    	OUT_RING(0 | BASE_ADDRESS_MODIFY);  /* media base addr, don't care */
-   	OUT_RING(0x10000000 | BASE_ADDRESS_MODIFY);  /* general state max addr, disabled */
-   	OUT_RING(0x10000000 | BASE_ADDRESS_MODIFY);  /* media object state max addr, disabled */
+	/* general state max addr, disabled */
+   	OUT_RING(0x10000000 | BASE_ADDRESS_MODIFY);
+	/* media object state max addr, disabled */
+   	OUT_RING(0x10000000 | BASE_ADDRESS_MODIFY);
 
-   /* Set system instruction pointer */
+	/* Set system instruction pointer */
    	OUT_RING(BRW_STATE_SIP | 0);
-   	OUT_RING(state_base_offset + sip_kernel_offset); /* system instruction pointer */
+   	OUT_RING(state_base_offset + sip_kernel_offset);
 	OUT_RING(MI_NOOP);
 	ADVANCE_LP_RING();
-   }
-   {
+    }
+    {
 	BEGIN_LP_RING(26);
-   /* Pipe control */
+	/* Pipe control */
    	OUT_RING(BRW_PIPE_CONTROL |
-	    BRW_PIPE_CONTROL_NOWRITE |
-	    BRW_PIPE_CONTROL_IS_FLUSH |
-	    2);
+		 BRW_PIPE_CONTROL_NOWRITE |
+		 BRW_PIPE_CONTROL_IS_FLUSH |
+		 2);
    	OUT_RING(0);			       /* Destination address */
    	OUT_RING(0);			       /* Immediate data low DW */
    	OUT_RING(0);			       /* Immediate data high DW */
 
-   /* Binding table pointers */
+	/* Binding table pointers */
    	OUT_RING(BRW_3DSTATE_BINDING_TABLE_POINTERS | 4);
    	OUT_RING(0); /* vs */
    	OUT_RING(0); /* gs */
    	OUT_RING(0); /* clip */
    	OUT_RING(0); /* sf */
-   /* Only the PS uses the binding table */
+	/* Only the PS uses the binding table */
    	OUT_RING(state_base_offset + binding_table_offset); /* ps */
 
-   /* The drawing rectangle clipping is always on.  Set it to values that
-    * shouldn't do any clipping.
-    */
-   	OUT_RING(BRW_3DSTATE_DRAWING_RECTANGLE | 2);	/* XXX 3 for BLC or CTG */
+	/* The drawing rectangle clipping is always on.  Set it to values that
+	 * shouldn't do any clipping.
+	 */
+   	OUT_RING(BRW_3DSTATE_DRAWING_RECTANGLE | 2); /* XXX 3 for BLC or CTG */
    	OUT_RING(0x00000000);	/* ymin, xmin */
    	OUT_RING((pScrn->virtualX - 1) |
  	         (pScrn->virtualY - 1) << 16); /* ymax, xmax */
    	OUT_RING(0x00000000);	/* yorigin, xorigin */
 
-   /* skip the depth buffer */
-   /* skip the polygon stipple */
-   /* skip the polygon stipple offset */
-   /* skip the line stipple */
-   
-   /* Set the pointers to the 3d pipeline state */
+	/* skip the depth buffer */
+	/* skip the polygon stipple */
+	/* skip the polygon stipple offset */
+	/* skip the line stipple */
+
+	/* Set the pointers to the 3d pipeline state */
    	OUT_RING(BRW_3DSTATE_PIPELINED_POINTERS | 5);
    	OUT_RING(state_base_offset + vs_offset);  /* 32 byte aligned */
-   	OUT_RING(BRW_GS_DISABLE);		     /* disable GS, resulting in passthrough */
-   	OUT_RING(BRW_CLIP_DISABLE);		     /* disable CLIP, resulting in passthrough */
+   	OUT_RING(BRW_GS_DISABLE);   /* disable GS, resulting in passthrough */
+   	OUT_RING(BRW_CLIP_DISABLE); /* disable CLIP, resulting in passthrough */
    	OUT_RING(state_base_offset + sf_offset);  /* 32 byte aligned */
    	OUT_RING(state_base_offset + wm_offset);  /* 32 byte aligned */
    	OUT_RING(state_base_offset + cc_offset);  /* 64 byte aligned */
 
-   /* URB fence */
+	/* URB fence */
    	OUT_RING(BRW_URB_FENCE |
         	 UF0_CS_REALLOC |
 	    	 UF0_SF_REALLOC |
@@ -906,27 +933,28 @@ I965EXAPrepareComposite(int op, PicturePtr pSrcPicture,
    	OUT_RING(((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) |
 	     	 ((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT));
 
-   /* Constant buffer state */
+	/* Constant buffer state */
    	OUT_RING(BRW_CS_URB_STATE | 0);
-   	OUT_RING(((URB_CS_ENTRY_SIZE - 1) << 4) | /* URB Entry Allocation Size */
-	    	 (URB_CS_ENTRIES << 0));	     /* Number of URB Entries */
+   	OUT_RING(((URB_CS_ENTRY_SIZE - 1) << 4) |
+	    	 (URB_CS_ENTRIES << 0));
 	ADVANCE_LP_RING();
-   }
-   {
+    }
+    {
         int nelem = pMask ? 3: 2;
    	BEGIN_LP_RING(pMask?12:10);
-   /* Set up the pointer to our vertex buffer */
-   	OUT_RING(BRW_3DSTATE_VERTEX_BUFFERS | 3); 
+	/* Set up the pointer to our vertex buffer */
+   	OUT_RING(BRW_3DSTATE_VERTEX_BUFFERS | 3);
    	OUT_RING((0 << VB0_BUFFER_INDEX_SHIFT) |
 	    	 VB0_VERTEXDATA |
-	    	 ((4 * 2 * nelem) << VB0_BUFFER_PITCH_SHIFT)); 
+	    	 ((4 * 2 * nelem) << VB0_BUFFER_PITCH_SHIFT));
    	OUT_RING(state_base_offset + vb_offset);
    	OUT_RING(2); // max index, prim has 4 coords
    	OUT_RING(0); // ignore for VERTEXDATA, but still there
 
-   /* Set up our vertex elements, sourced from the single vertex buffer. */
-   	OUT_RING(BRW_3DSTATE_VERTEX_ELEMENTS | ((2 * nelem) - 1));  
-   /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
+	/* Set up our vertex elements, sourced from the single vertex buffer.
+	 */
+   	OUT_RING(BRW_3DSTATE_VERTEX_ELEMENTS | ((2 * nelem) - 1));
+	/* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
    	OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
 	    	 VE0_VALID |
 	    	 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
@@ -936,7 +964,7 @@ I965EXAPrepareComposite(int op, PicturePtr pSrcPicture,
 	     	 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
 	    	 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
 	    	 (0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
-   /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
+	/* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
    	OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
 	    	 VE0_VALID |
 	    	 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
@@ -948,30 +976,30 @@ I965EXAPrepareComposite(int op, PicturePtr pSrcPicture,
 	    	 (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
 
    	if (pMask) {
-   		OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
-	    		 VE0_VALID |
-	    		 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
-	    		 (16 << VE0_OFFSET_SHIFT));
-		OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
-	    		 (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
-	    		 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
-	    		 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
-	    		 (8 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); 
+	    OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
+		     VE0_VALID |
+		     (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
+		     (16 << VE0_OFFSET_SHIFT));
+	    OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+		     (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+		     (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
+		     (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
+		     (8 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
    	}
-   
+
    	ADVANCE_LP_RING();
-   }
+    }
 
 #ifdef I830DEBUG
     ErrorF("try to sync to show any errors...");
     I830Sync(pScrn);
 #endif
     return TRUE;
-}	
+}
 
 void
-I965EXAComposite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
-		int dstX, int dstY, int w, int h)
+i965_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
+	       int dstX, int dstY, int w, int h)
 {
     ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
     I830Ptr pI830 = I830PTR(pScrn);
@@ -1039,12 +1067,12 @@ I965EXAComposite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
     }
     vb[i++] = (float)dstX;
     vb[i++] = (float)dstY;
-   
+
     {
       BEGIN_LP_RING(6);
-      OUT_RING(BRW_3DPRIMITIVE | 
+      OUT_RING(BRW_3DPRIMITIVE |
 	       BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL |
-	       (_3DPRIM_RECTLIST << BRW_3DPRIMITIVE_TOPOLOGY_SHIFT) | 
+	       (_3DPRIM_RECTLIST << BRW_3DPRIMITIVE_TOPOLOGY_SHIFT) |
 	       (0 << 9) |  /* CTG - indirect vertex count */
 	       4);
       OUT_RING(3);  /* vertex count per instance */