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authorZhenyu Wang <zhenyu.z.wang@intel.com>2008-01-09 21:27:42 +0800
committerZhenyu Wang <zhenyu.z.wang@intel.com>2008-01-09 21:27:42 +0800
commit2f0c0427dc4113bac64cda07c6365df1f0637697 (patch)
tree429649e41e436b2719936149de9138a084adb5df /src/i965_video.c
parent139e9affdd49dcbe08e260a0a2bd001de16566e6 (diff)
Update PIPELINE_SELECT instruction and surface state format for new chipset
Diffstat (limited to 'src/i965_video.c')
-rw-r--r--src/i965_video.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/i965_video.c b/src/i965_video.c
index 03572703..928b52b7 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -509,7 +509,10 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
{
BEGIN_LP_RING(12);
/* Match Mesa driver setup */
- OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ if (IS_IGD_GM(pI830))
+ OUT_RING(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ else
+ OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
/* Mesa does this. Who knows... */
OUT_RING(BRW_CS_URB_STATE | 0);