diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2010-05-19 09:30:02 +0100 |
|---|---|---|
| committer | Owain G. Ainsworth <oga@openbsd.org> | 2010-05-25 16:27:09 +0100 |
| commit | 875e5ab72623a419d4521aa95ad87bbcf4973219 (patch) | |
| tree | af8898451430c436e73900a33a0202a7b9ba7e63 /src/i965_video.c | |
| parent | 3effdababd831a4956f8dd2d956cf0efd3f37cfc (diff) | |
Kill paranoid assertions on every write into the batchbuffer.
On my PineView box these represent ~5% overhead on x11perf text:
Before:
16000000 trep @ 0.0020 msec (495000.0/sec): Char in 80-char aa line (Charter 10)
12000000 trep @ 0.0022 msec (461000.0/sec): Char in 80-char rgb line (Charter 10)
After:
16000000 trep @ 0.0020 msec (511000.0/sec): Char in 80-char aa line (Charter 10)
16000000 trep @ 0.0021 msec (480000.0/sec): Char in 80-char rgb line (Charter 10)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Owain G. Ainsworth <oga@openbsd.org>
Diffstat (limited to 'src/i965_video.c')
| -rw-r--r-- | src/i965_video.c | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/src/i965_video.c b/src/i965_video.c index c5378608..1beea7d6 100644 --- a/src/i965_video.c +++ b/src/i965_video.c @@ -779,18 +779,12 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * bind_bo, int n_src_surf) urb_cs_start = urb_sf_start + urb_sf_size; urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE; - ATOMIC_BATCH(2); OUT_BATCH(MI_FLUSH | MI_STATE_INSTRUCTION_CACHE_FLUSH | BRW_MI_GLOBAL_SNAPSHOT_RESET); OUT_BATCH(MI_NOOP); - ADVANCE_BATCH(); /* brw_debug (scrn, "before base address modify"); */ - if (IS_IGDNG(intel)) - ATOMIC_BATCH(14); - else - ATOMIC_BATCH(12); /* Match Mesa driver setup */ if (IS_G4X(intel) || IS_IGDNG(intel)) OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D); @@ -834,9 +828,6 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * bind_bo, int n_src_surf) OUT_RELOC(intel->video.gen4_sip_kernel_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); - OUT_BATCH(MI_NOOP); - ADVANCE_BATCH(); - /* brw_debug (scrn, "after base address modify"); */ if (IS_IGDNG(intel)) @@ -844,10 +835,6 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * bind_bo, int n_src_surf) else pipe_ctl = BRW_PIPE_CONTROL_NOWRITE | BRW_PIPE_CONTROL_IS_FLUSH; - ATOMIC_BATCH(38); - - OUT_BATCH(MI_NOOP); - /* Pipe control */ OUT_BATCH(BRW_PIPE_CONTROL | pipe_ctl | 2); OUT_BATCH(0); /* Destination address */ @@ -971,9 +958,6 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * bind_bo, int n_src_surf) VE1_VFCOMPONENT_3_SHIFT) | (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); } - - OUT_BATCH(MI_NOOP); /* pad to quadword */ - ADVANCE_BATCH(); } void @@ -1220,7 +1204,6 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn, i965_emit_video_setup(scrn, bind_bo, n_src_surf); - ATOMIC_BATCH(12); /* Set up the pointer to our vertex buffer */ OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | 3); /* four 32-bit floats per vertex */ @@ -1242,7 +1225,6 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn, OUT_BATCH(0); /* start instance location */ OUT_BATCH(0); /* index buffer offset, ignored */ OUT_BATCH(MI_NOOP); - ADVANCE_BATCH(); intel_batch_end_atomic(scrn); |