diff options
| author | Zou Nan hai <nanhai.zou@intel.com> | 2010-11-01 13:23:35 +0800 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-11-01 10:37:51 +0000 |
| commit | 5bed685f765671d63642b24e17abd70579c40ddf (patch) | |
| tree | 11db10f673f180dd583752b890a41c3da73aa4d4 /src/intel_batchbuffer.c | |
| parent | 6ec3ff134baeac33d9d5821695d5f80843a96c91 (diff) | |
add BLT ring support
gen6+ platform has a BLT engine with seperate
command streamer to support BLT commands.
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
[ickle: merge trivial conflict]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'src/intel_batchbuffer.c')
| -rw-r--r-- | src/intel_batchbuffer.c | 51 |
1 files changed, 30 insertions, 21 deletions
diff --git a/src/intel_batchbuffer.c b/src/intel_batchbuffer.c index d2653d48..fec52819 100644 --- a/src/intel_batchbuffer.c +++ b/src/intel_batchbuffer.c @@ -147,27 +147,33 @@ void intel_batch_emit_flush(ScrnInfoPtr scrn) assert (!intel->in_batch_atomic); - if ((INTEL_INFO(intel)->gen >= 60)) { - BEGIN_BATCH(4); - OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2)); /* Mesa does so */ - OUT_BATCH(BRW_PIPE_CONTROL_IS_FLUSH | - BRW_PIPE_CONTROL_WC_FLUSH | - BRW_PIPE_CONTROL_DEPTH_CACHE_FLUSH | - BRW_PIPE_CONTROL_NOWRITE); - OUT_BATCH(0); /* write address */ - OUT_BATCH(0); /* write data */ - ADVANCE_BATCH(); + /* Big hammer, look to the pipelined flushes in future. */ + if (intel->current_batch == BLT_BATCH) { + BEGIN_BATCH_BLT(4); + OUT_BATCH(MI_FLUSH_DW | 2); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + } else if ((INTEL_INFO(intel)->gen >= 60)) { + BEGIN_BATCH(4); + OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2)); /* Mesa does so */ + OUT_BATCH(BRW_PIPE_CONTROL_IS_FLUSH | + BRW_PIPE_CONTROL_WC_FLUSH | + BRW_PIPE_CONTROL_DEPTH_CACHE_FLUSH | + BRW_PIPE_CONTROL_NOWRITE); + OUT_BATCH(0); /* write address */ + OUT_BATCH(0); /* write data */ + ADVANCE_BATCH(); } else { - /* Big hammer, look to the pipelined flushes in future. */ - flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE; - if (INTEL_INFO(intel)->gen >= 40) - flags = 0; - - BEGIN_BATCH(1); - OUT_BATCH(MI_FLUSH | flags); - ADVANCE_BATCH(); - } + flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE; + if (INTEL_INFO(intel)->gen >= 40) + flags = 0; + BEGIN_BATCH(1); + OUT_BATCH(MI_FLUSH | flags); + ADVANCE_BATCH(); + } intel_batch_do_flush(scrn); } @@ -204,8 +210,11 @@ void intel_batch_submit(ScrnInfoPtr scrn, int flush) ret = dri_bo_subdata(intel->batch_bo, 0, intel->batch_used*4, intel->batch_ptr); if (ret == 0) - ret = dri_bo_exec(intel->batch_bo, intel->batch_used*4, - NULL, 0, 0xffffffff); + ret = drm_intel_bo_mrb_exec(intel->batch_bo, + intel->batch_used*4, + NULL, 0, 0xffffffff, + intel->current_batch); + if (ret != 0) { if (ret == -EIO) { static int once; |