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authorChris Wilson <chris@chris-wilson.co.uk>2011-04-07 15:09:30 +0100
committerChris Wilson <chris@chris-wilson.co.uk>2011-04-07 15:09:30 +0100
commit25521900df11bc71020ee80db2223f979bec5ec6 (patch)
tree4bdbd1b4e1391ea2665f28471be5f51a5c1e9e79 /src/intel_batchbuffer.c
parentad22003033eb502474ae538a97e3b42cf8f83880 (diff)
gen6: Invalidate texture cache
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'src/intel_batchbuffer.c')
-rw-r--r--src/intel_batchbuffer.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/intel_batchbuffer.c b/src/intel_batchbuffer.c
index 2e1b7d96..282d8ab1 100644
--- a/src/intel_batchbuffer.c
+++ b/src/intel_batchbuffer.c
@@ -157,6 +157,7 @@ void intel_batch_emit_flush(ScrnInfoPtr scrn)
BEGIN_BATCH(4);
OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
OUT_BATCH(BRW_PIPE_CONTROL_WC_FLUSH |
+ BRW_PIPE_CONTROL_TC_FLUSH |
BRW_PIPE_CONTROL_NOWRITE);
OUT_BATCH(0); /* write address */
OUT_BATCH(0); /* write data */