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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2012-07-06 09:42:37 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2012-07-06 10:06:16 +0100 |
| commit | 5784e0f21dc91f33c99a507105a0695cc53d6574 (patch) | |
| tree | 3b4a4d1823166a57e8a88a537eb5ee097398bf16 /src/intel_driver.c | |
| parent | 1ee10cc3b2aa0888753eeb25c7fde7296a3c92eb (diff) | |
Allow matching against any device supported by drm/i915
However we cannot enable acceleration if we do not recognise its
hardware layout or instruction set.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'src/intel_driver.c')
| -rw-r--r-- | src/intel_driver.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/intel_driver.c b/src/intel_driver.c index 77611f53..f2770d6c 100644 --- a/src/intel_driver.c +++ b/src/intel_driver.c @@ -417,6 +417,9 @@ static Bool has_relaxed_fencing(struct intel_screen_private *intel) static Bool can_accelerate_blt(struct intel_screen_private *intel) { + if (INTEL_INFO(intel)->gen == 0) + return FALSE; + if (0 && (IS_I830(intel) || IS_845G(intel))) { /* These pair of i8xx chipsets have a crippling erratum * that prevents the use of a PTE entry by the BLT |