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| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-09-30 10:58:49 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-09-30 11:02:22 +0800 |
| commit | 345c963e443ec325f1ff530512a356ddb318ff70 (patch) | |
| tree | e90d1cabae15955d1eaf73436206682e0f34eb05 /src/intel_driver.h | |
| parent | d4c013cb9d92d2959c9a98eca20e43ab14ae22e3 (diff) | |
Always use tiling on Sandybridge
Sandybridge requires kind of buffer must be tiling, like depth.
And we would or have all tiling cases handled fine. So not allow
user to turn off tiling on Sandybridge+ may be fine.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'src/intel_driver.h')
| -rw-r--r-- | src/intel_driver.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/intel_driver.h b/src/intel_driver.h index b55c8c96..31b30090 100644 --- a/src/intel_driver.h +++ b/src/intel_driver.h @@ -264,6 +264,8 @@ /* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */ #define SUPPORTS_YTILING(pI810) (IS_I965G(intel)) +#define ALWAYS_TILING(intel) (IS_GEN6(intel)) + extern SymTabRec *intel_chipsets; struct intel_chipset { |