diff options
| author | Rodrigo Vivi <rodrigo.vivi@gmail.com> | 2013-05-13 17:56:29 -0300 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2013-05-14 09:34:42 +0100 |
| commit | ee96de8b1e7e4a305ee31c0ece1d9d38df8328f9 (patch) | |
| tree | 4156a063bcff6cf711c27b5c301f395b482afb9d /src/intel_driver.h | |
| parent | 979d2f8d0038aa621e1c75200b10a3819e024a66 (diff) | |
Fix Haswell GT3 names.
When publishing first HSW ids we weren't allowed to use "GT3" codname.
But this is the correct codname and Mesa is using it already.
So to avoid people getting confused why in Mesa it is called GT3 and here
it is called GT2_PLUS let's fix this name in a standard and correct way.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Diffstat (limited to 'src/intel_driver.h')
| -rw-r--r-- | src/intel_driver.h | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/src/intel_driver.h b/src/intel_driver.h index d109c7e7..4b05e255 100644 --- a/src/intel_driver.h +++ b/src/intel_driver.h @@ -194,55 +194,55 @@ #define PCI_CHIP_HASWELL_D_GT1 0x0402 #define PCI_CHIP_HASWELL_D_GT2 0x0412 -#define PCI_CHIP_HASWELL_D_GT2_PLUS 0x0422 +#define PCI_CHIP_HASWELL_D_GT3 0x0422 #define PCI_CHIP_HASWELL_M_GT1 0x0406 #define PCI_CHIP_HASWELL_M_GT2 0x0416 -#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426 +#define PCI_CHIP_HASWELL_M_GT3 0x0426 #define PCI_CHIP_HASWELL_S_GT1 0x040A #define PCI_CHIP_HASWELL_S_GT2 0x041A -#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A +#define PCI_CHIP_HASWELL_S_GT3 0x042A #define PCI_CHIP_HASWELL_GT1_RSVD 0x040E #define PCI_CHIP_HASWELL_GT2_RSVD 0x041E -#define PCI_CHIP_HASWELL_GT2_PLUS_RSVD 0x042E +#define PCI_CHIP_HASWELL_GT3_RSVD 0x042E #define PCI_CHIP_HASWELL_SDV_D_GT1 0x0C02 #define PCI_CHIP_HASWELL_SDV_D_GT2 0x0C12 -#define PCI_CHIP_HASWELL_SDV_D_GT2_PLUS 0x0C22 +#define PCI_CHIP_HASWELL_SDV_D_GT3 0x0C22 #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 -#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26 +#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26 #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A -#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A +#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A #define PCI_CHIP_HASWELL_SDV_GT1_RSVD 0x0C0E #define PCI_CHIP_HASWELL_SDV_GT2_RSVD 0x0C1E -#define PCI_CHIP_HASWELL_SDV_GT2_PLUS_RSVD 0x0C2E +#define PCI_CHIP_HASWELL_SDV_GT3_RSVD 0x0C2E #define PCI_CHIP_HASWELL_ULT_D_GT1 0x0A02 #define PCI_CHIP_HASWELL_ULT_D_GT2 0x0A12 -#define PCI_CHIP_HASWELL_ULT_D_GT2_PLUS 0x0A22 +#define PCI_CHIP_HASWELL_ULT_D_GT3 0x0A22 #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 -#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26 +#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26 #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A -#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A +#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A #define PCI_CHIP_HASWELL_ULT_GT1_RSVD 0x0A0E #define PCI_CHIP_HASWELL_ULT_GT2_RSVD 0x0A1E -#define PCI_CHIP_HASWELL_ULT_GT2_PLUS_RSVD 0x0A2E +#define PCI_CHIP_HASWELL_ULT_GT3_RSVD 0x0A2E #define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D02 #define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D12 -#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS 0x0D22 +#define PCI_CHIP_HASWELL_CRW_D_GT3 0x0D22 #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 -#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26 +#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26 #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A -#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A +#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A #define PCI_CHIP_HASWELL_CRW_GT1_RSVD 0x0D0E #define PCI_CHIP_HASWELL_CRW_GT2_RSVD 0x0D1E -#define PCI_CHIP_HASWELL_CRW_GT2_PLUS_RSVD 0x0D2E +#define PCI_CHIP_HASWELL_CRW_GT3_RSVD 0x0D2E #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 #define PCI_CHIP_VALLEYVIEW_1 0x0f31 |