diff options
| author | Rodrigo Vivi <rodrigo.vivi@gmail.com> | 2013-05-13 17:56:30 -0300 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2013-05-14 09:34:58 +0100 |
| commit | 3ee42de066e4629f78e254c27d07dc33e16dbc02 (patch) | |
| tree | 38f3e5a46f731417486ce25fc8004bb5e1e8863f /src/intel_driver.h | |
| parent | ee96de8b1e7e4a305ee31c0ece1d9d38df8328f9 (diff) | |
Adding more reserved PCI IDs for Haswell.
As Chris mentioned there is a tendency for us to find out more
PCI IDs only when users report. So let's add all new reserved Haswell IDs.
I didn't have better names for this reserved ids and didn't want to use rsvd1
and rsvd2 groups, so I decided to use "B" and "E" that stands for the last
id digit.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Diffstat (limited to 'src/intel_driver.h')
| -rw-r--r-- | src/intel_driver.h | 36 |
1 files changed, 24 insertions, 12 deletions
diff --git a/src/intel_driver.h b/src/intel_driver.h index 4b05e255..32f623b2 100644 --- a/src/intel_driver.h +++ b/src/intel_driver.h @@ -201,9 +201,12 @@ #define PCI_CHIP_HASWELL_S_GT1 0x040A #define PCI_CHIP_HASWELL_S_GT2 0x041A #define PCI_CHIP_HASWELL_S_GT3 0x042A -#define PCI_CHIP_HASWELL_GT1_RSVD 0x040E -#define PCI_CHIP_HASWELL_GT2_RSVD 0x041E -#define PCI_CHIP_HASWELL_GT3_RSVD 0x042E +#define PCI_CHIP_HASWELL_B_GT1 0x040B +#define PCI_CHIP_HASWELL_B_GT2 0x041B +#define PCI_CHIP_HASWELL_B_GT3 0x042B +#define PCI_CHIP_HASWELL_E_GT1 0x040E +#define PCI_CHIP_HASWELL_E_GT2 0x041E +#define PCI_CHIP_HASWELL_E_GT3 0x042E #define PCI_CHIP_HASWELL_SDV_D_GT1 0x0C02 #define PCI_CHIP_HASWELL_SDV_D_GT2 0x0C12 @@ -214,9 +217,12 @@ #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A #define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A -#define PCI_CHIP_HASWELL_SDV_GT1_RSVD 0x0C0E -#define PCI_CHIP_HASWELL_SDV_GT2_RSVD 0x0C1E -#define PCI_CHIP_HASWELL_SDV_GT3_RSVD 0x0C2E +#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0E +#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1E +#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2E +#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E +#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E +#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E #define PCI_CHIP_HASWELL_ULT_D_GT1 0x0A02 #define PCI_CHIP_HASWELL_ULT_D_GT2 0x0A12 @@ -227,9 +233,12 @@ #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A #define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A -#define PCI_CHIP_HASWELL_ULT_GT1_RSVD 0x0A0E -#define PCI_CHIP_HASWELL_ULT_GT2_RSVD 0x0A1E -#define PCI_CHIP_HASWELL_ULT_GT3_RSVD 0x0A2E +#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B +#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B +#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B +#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E +#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E +#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E #define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D02 #define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D12 @@ -240,9 +249,12 @@ #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A #define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A -#define PCI_CHIP_HASWELL_CRW_GT1_RSVD 0x0D0E -#define PCI_CHIP_HASWELL_CRW_GT2_RSVD 0x0D1E -#define PCI_CHIP_HASWELL_CRW_GT3_RSVD 0x0D2E +#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B +#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B +#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B +#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E +#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E +#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 #define PCI_CHIP_VALLEYVIEW_1 0x0f31 |