diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2013-04-27 12:06:30 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2013-04-27 12:09:07 +0100 |
| commit | ab576a42650d8a743dd91108f774c220d866de95 (patch) | |
| tree | 4c4c57003e22cf66c2b5e61f8c67c7bbf5a33492 /src/intel_driver.h | |
| parent | 7dfb359677027310f4617b49f3da2321727a076f (diff) | |
Add all reserved PCI-IDs for Haswell
There is a tendency for a product to ship based on a 'reserved' PCI-ID
prior to us being notified about it. In other words, the first we find
out about such a product is when customers start complaining about their
shiny new hardware not being supported...
References: https://bugs.freedesktop.org/show_bug.cgi?id=63701
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'src/intel_driver.h')
| -rw-r--r-- | src/intel_driver.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/intel_driver.h b/src/intel_driver.h index 0dda5b1f..d109c7e7 100644 --- a/src/intel_driver.h +++ b/src/intel_driver.h @@ -201,6 +201,10 @@ #define PCI_CHIP_HASWELL_S_GT1 0x040A #define PCI_CHIP_HASWELL_S_GT2 0x041A #define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A +#define PCI_CHIP_HASWELL_GT1_RSVD 0x040E +#define PCI_CHIP_HASWELL_GT2_RSVD 0x041E +#define PCI_CHIP_HASWELL_GT2_PLUS_RSVD 0x042E + #define PCI_CHIP_HASWELL_SDV_D_GT1 0x0C02 #define PCI_CHIP_HASWELL_SDV_D_GT2 0x0C12 #define PCI_CHIP_HASWELL_SDV_D_GT2_PLUS 0x0C22 @@ -210,6 +214,10 @@ #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A #define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A +#define PCI_CHIP_HASWELL_SDV_GT1_RSVD 0x0C0E +#define PCI_CHIP_HASWELL_SDV_GT2_RSVD 0x0C1E +#define PCI_CHIP_HASWELL_SDV_GT2_PLUS_RSVD 0x0C2E + #define PCI_CHIP_HASWELL_ULT_D_GT1 0x0A02 #define PCI_CHIP_HASWELL_ULT_D_GT2 0x0A12 #define PCI_CHIP_HASWELL_ULT_D_GT2_PLUS 0x0A22 @@ -219,6 +227,10 @@ #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A #define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A +#define PCI_CHIP_HASWELL_ULT_GT1_RSVD 0x0A0E +#define PCI_CHIP_HASWELL_ULT_GT2_RSVD 0x0A1E +#define PCI_CHIP_HASWELL_ULT_GT2_PLUS_RSVD 0x0A2E + #define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D02 #define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D12 #define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS 0x0D22 @@ -228,6 +240,9 @@ #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A #define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A +#define PCI_CHIP_HASWELL_CRW_GT1_RSVD 0x0D0E +#define PCI_CHIP_HASWELL_CRW_GT2_RSVD 0x0D1E +#define PCI_CHIP_HASWELL_CRW_GT2_PLUS_RSVD 0x0D2E #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 #define PCI_CHIP_VALLEYVIEW_1 0x0f31 |