diff options
| author | Eric Anholt <eric@anholt.net> | 2011-05-06 12:56:53 -0700 |
|---|---|---|
| committer | Owain G. Ainsworth <oga@openbsd.org> | 2011-05-30 00:14:20 +0100 |
| commit | eec59a69518f04684e7d77fc57528c1620c6024b (patch) | |
| tree | ea79be7ef243bb29dbcf1204655b05d7d27af619 /src/intel_driver.h | |
| parent | 49939c8c560a37c4e4f090271a5f97291faefccb (diff) | |
Store the chipset info struct in the PCI match struct, instead of a switch().
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit adf7bbd3a8758de6cdecbace42e399dd27188497)
Conflicts:
src/intel_module.c
(merges in an earlier s/igd/pineview s/igdng/ironlake commit)
Diffstat (limited to 'src/intel_driver.h')
| -rw-r--r-- | src/intel_driver.h | 61 |
1 files changed, 37 insertions, 24 deletions
diff --git a/src/intel_driver.h b/src/intel_driver.h index 3bbc0214..6aa39546 100644 --- a/src/intel_driver.h +++ b/src/intel_driver.h @@ -76,11 +76,11 @@ #define PCI_CHIP_I945_GME_BRIDGE 0x27AC #endif -#ifndef PCI_CHIP_IGD_GM -#define PCI_CHIP_IGD_GM 0xA011 -#define PCI_CHIP_IGD_GM_BRIDGE 0xA010 -#define PCI_CHIP_IGD_G 0xA001 -#define PCI_CHIP_IGD_G_BRIDGE 0xA000 +#ifndef PCI_CHIP_PINEVIEW_M +#define PCI_CHIP_PINEVIEW_M 0xA011 +#define PCI_CHIP_PINEVIEW_M_BRIDGE 0xA010 +#define PCI_CHIP_PINEVIEW_G 0xA001 +#define PCI_CHIP_PINEVIEW_G_BRIDGE 0xA000 #endif #ifndef PCI_CHIP_G35_G @@ -133,9 +133,9 @@ #define PCI_CHIP_GM45_BRIDGE 0x2A40 #endif -#ifndef PCI_CHIP_IGD_E_G -#define PCI_CHIP_IGD_E_G 0x2E02 -#define PCI_CHIP_IGD_E_G_BRIDGE 0x2E00 +#ifndef PCI_CHIP_G45_E_G +#define PCI_CHIP_G45_E_G 0x2E02 +#define PCI_CHIP_G45_E_G_BRIDGE 0x2E00 #endif #ifndef PCI_CHIP_G45_G @@ -163,21 +163,34 @@ #define PCI_CHIP_B43_G1_BRIDGE 0x2E90 #endif -#ifndef PCI_CHIP_IGDNG_D_G -#define PCI_CHIP_IGDNG_D_G 0x0042 -#define PCI_CHIP_IGDNG_D_G_BRIDGE 0x0040 +#ifndef PCI_CHIP_IRONLAKE_D_G +#define PCI_CHIP_IRONLAKE_D_G 0x0042 +#define PCI_CHIP_IRONLAKE_D_G_BRIDGE 0x0040 #endif -#ifndef PCI_CHIP_IGDNG_M_G -#define PCI_CHIP_IGDNG_M_G 0x0046 -#define PCI_CHIP_IGDNG_M_G_BRIDGE 0x0044 +#ifndef PCI_CHIP_IRONLAKE_M_G +#define PCI_CHIP_IRONLAKE_M_G 0x0046 +#define PCI_CHIP_IRONLAKE_M_G_BRIDGE 0x0044 #endif -#ifndef PCI_CHIP_SANDYBRIDGE -#define PCI_CHIP_SANDYBRIDGE 0x0102 -#define PCI_CHIP_SANDYBRIDGE_BRIDGE 0x0100 -#define PCI_CHIP_SANDYBRIDGE_M 0x0106 -#define PCI_CHIP_SANDYBRIDGE_BRIDGE_M 0x0104 +#ifndef PCI_CHIP_SANDYBRIDGE_BRIDGE +#define PCI_CHIP_SANDYBRIDGE_BRIDGE 0x0100 /* Desktop */ +#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 +#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112 +#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122 +#define PCI_CHIP_SANDYBRIDGE_BRIDGE_M 0x0104 /* Mobile */ +#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 +#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116 +#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126 +#define PCI_CHIP_SANDYBRIDGE_BRIDGE_S 0x0108 /* Server */ +#define PCI_CHIP_SANDYBRIDGE_S_GT 0x010A + +#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 +#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166 +#define PCI_CHIP_IVYBRIDGE_D_GT1 0x0152 +#define PCI_CHIP_IVYBRIDGE_D_GT2 0x0162 +#define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a + #endif #define I85X_CAPID 0x44 @@ -216,16 +229,16 @@ #define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM) #define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G) #define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME) - #define IS_IGDGM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_GM) - #define IS_IGDG(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_G) + #define IS_IGDGM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_PINEVIEW_M) + #define IS_IGDG(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_PINEVIEW_G) #define IS_IGD(pI810) (IS_IGDG(pI810) || IS_IGDGM(pI810)) #define IS_GM45(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_GM45_GM) - #define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_B43_G || IS_GM45(pI810)) + #define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_B43_G || IS_GM45(pI810)) #define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME) #define IS_965_Q(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q) -#define IS_IGDNG_D(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_D_G) -#define IS_IGDNG_M(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_M_G) +#define IS_IGDNG_D(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IRONLAKE_D_G) +#define IS_IGDNG_M(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IRONLAKE_M_G) #define IS_IGDNG(pI810) (IS_IGDNG_D(pI810) || IS_IGDNG_M(pI810)) #define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || \ DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || \ |