diff options
| author | Owain G. Ainsworth <oga@openbsd.org> | 2011-03-16 19:12:27 +0000 |
|---|---|---|
| committer | Owain G. Ainsworth <oga@openbsd.org> | 2011-03-16 19:12:27 +0000 |
| commit | 2246934a0ff1796f2d28b1773c0927949661d791 (patch) | |
| tree | a5ba45e11612afc339916787a2ad1de15ac6faca /src/intel_memory.c | |
| parent | 70bd10332e5a71e91cc59a36b4debf9ff2abae08 (diff) | |
Include a chipset generation number to clarify device specific paths.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
(cherry picked from commit 4083197a44d1a1a05d33654b3c7d6e96d7472fe7)
Conflicts:
src/intel_driver.c
src/intel_driver.h
src/intel_module.c
src/intel_video.c
(oga notes: few other things had to be pulled in to get this to work)
Diffstat (limited to 'src/intel_memory.c')
| -rw-r--r-- | src/intel_memory.c | 29 |
1 files changed, 14 insertions, 15 deletions
diff --git a/src/intel_memory.c b/src/intel_memory.c index 6664be66..e619f674 100644 --- a/src/intel_memory.c +++ b/src/intel_memory.c @@ -106,14 +106,14 @@ unsigned long intel_get_fence_size(intel_screen_private *intel, unsigned long si unsigned long i; unsigned long start; - if (IS_I965G(intel)) { + if (INTEL_INFO(intel)->gen >= 40) { /* The 965 can have fences at any page boundary. */ return ALIGN(size, GTT_PAGE_SIZE); } else { /* Align the size to a power of two greater than the smallest fence * size. */ - if (IS_I9XX(intel)) + if (IS_GEN3(intel)) start = MB(1); else start = KB(512); @@ -138,8 +138,8 @@ intel_get_fence_pitch(intel_screen_private *intel, unsigned long pitch, if (format == I915_TILING_NONE) return pitch; - /* 965 is flexible */ - if (IS_I965G(intel)) + /* 965+ is flexible */ + if (INTEL_INFO(intel)->gen >= 40) return ALIGN(pitch, tile_width); /* Pre-965 needs power of two tile width */ @@ -156,17 +156,16 @@ intel_check_display_stride(ScrnInfoPtr scrn, int stride, Bool tiling) /* 8xx spec has always 8K limit, but tests show larger limit in non-tiling mode, which makes large monitor work. */ - if (IS_I8XX(intel) && tiling) - limit = KB(8); - - if (IS_I915(intel) && tiling) - limit = KB(8); - - if (IS_I965G(intel) && tiling) - limit = KB(16); - - if (IS_IGDNG(intel) && tiling) - limit = KB(32); + if (tiling) { + if (IS_GEN2(intel)) + limit = KB(8); + else if (IS_GEN3(intel)) + limit = KB(8); + else if (IS_GEN4(intel)) + limit = KB(16); + else + limit = KB(32); + } if (stride <= limit) return TRUE; |