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authorChris Wilson <chris@chris-wilson.co.uk>2010-10-29 11:07:50 +0100
committerOwain G. Ainsworth <oga@openbsd.org>2011-03-16 21:38:40 +0000
commit75a854a7a86776789225743bb9d469f9fd9033da (patch)
tree0bb5e602c777d8502e98324172ac667ee002173a /src/intel_memory.c
parent64d3e15611b1910fd0e825b0a0e407237d549c92 (diff)
uxa: Enable reduced fence sizes for i915
Depends on libdrm 362457715faacd3101929e5f0d8ae250d0ad09df (for HAS_RELAXED_FENCING define). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> (cherry picked from commit 6b3ce2e8701e7c3fcd30ca07fc13a2cdcf62560d) Signed-off-by: Owain G. Ainsworth <oga@openbsd.org>
Diffstat (limited to 'src/intel_memory.c')
-rw-r--r--src/intel_memory.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/intel_memory.c b/src/intel_memory.c
index af196fed..2b80df21 100644
--- a/src/intel_memory.c
+++ b/src/intel_memory.c
@@ -106,7 +106,7 @@ unsigned long intel_get_fence_size(intel_screen_private *intel, unsigned long si
unsigned long i;
unsigned long start;
- if (INTEL_INFO(intel)->gen >= 40) {
+ if (INTEL_INFO(intel)->gen >= 40 || intel->has_relaxed_fencing) {
/* The 965 can have fences at any page boundary. */
return ALIGN(size, GTT_PAGE_SIZE);
} else {
@@ -1317,11 +1317,17 @@ void intel_set_gem_max_sizes(ScrnInfoPtr scrn)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
struct drm_i915_gem_get_aperture aperture;
+ drm_i915_getparam_t gp;
+ int ret;
aperture.aper_available_size = 0;
- ioctl(intel->drmSubFD, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
+ drmIoctl(intel->drmSubFD, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
intel_set_max_bo_size(intel, &aperture);
intel_set_max_gtt_map_size(intel, &aperture);
intel_set_max_tiling_size(intel, &aperture);
+
+ gp.param = I915_PARAM_HAS_RELAXED_FENCING;
+ ret = drmIoctl(intel->drmSubFD, DRM_IOCTL_I915_GETPARAM, &gp);
+ intel->has_relaxed_fencing = ret == 0;
}