diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2012-09-13 22:15:14 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2012-09-14 21:51:36 +0100 |
| commit | fe78904a45979d47bb092ce37d321854e2418344 (patch) | |
| tree | 318ce933e3e8c19826510337f01d428a7d211095 /src/intel_module.c | |
| parent | 3b9259f7cedc179617bc24b3912d2d8d75c5a824 (diff) | |
Add basic support for ValleyView
Bind to the ValleyView SDV for verifying the render routines.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'src/intel_module.c')
| -rw-r--r-- | src/intel_module.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/intel_module.c b/src/intel_module.c index 65a91b1c..bc0b6d25 100644 --- a/src/intel_module.c +++ b/src/intel_module.c @@ -103,6 +103,10 @@ static const struct intel_device_info intel_ivybridge_info = { .gen = 70, }; +static const struct intel_device_info intel_valleyview_info = { + .gen = 70, +}; + static const struct intel_device_info intel_haswell_info = { .gen = 75, }; @@ -192,6 +196,7 @@ static const SymTabRec _intel_chipsets[] = { {PCI_CHIP_HASWELL_CRW_S_GT1, "Haswell CRW Server (GT1)" }, {PCI_CHIP_HASWELL_CRW_S_GT2, "Haswell CRW Server (GT2)" }, {PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, "Haswell CRW Server (GT2+)" }, + {PCI_CHIP_VALLEYVIEW_PO, "ValleyView PO board" }, {-1, NULL} }; #define NUM_CHIPSETS (sizeof(_intel_chipsets) / sizeof(_intel_chipsets[0])) @@ -301,6 +306,8 @@ static const struct pci_id_match intel_device_match[] = { INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_PO, &intel_valleyview_info ), + INTEL_DEVICE_MATCH (PCI_MATCH_ANY, &intel_generic_info ), { 0, 0, 0 }, }; |