diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2013-04-27 12:06:30 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2013-04-27 12:09:07 +0100 |
| commit | ab576a42650d8a743dd91108f774c220d866de95 (patch) | |
| tree | 4c4c57003e22cf66c2b5e61f8c67c7bbf5a33492 /src/intel_module.c | |
| parent | 7dfb359677027310f4617b49f3da2321727a076f (diff) | |
Add all reserved PCI-IDs for Haswell
There is a tendency for a product to ship based on a 'reserved' PCI-ID
prior to us being notified about it. In other words, the first we find
out about such a product is when customers start complaining about their
shiny new hardware not being supported...
References: https://bugs.freedesktop.org/show_bug.cgi?id=63701
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'src/intel_module.c')
| -rw-r--r-- | src/intel_module.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/intel_module.c b/src/intel_module.c index 4434ed07..73cfa973 100644 --- a/src/intel_module.c +++ b/src/intel_module.c @@ -277,6 +277,10 @@ static const struct pci_id_match intel_device_match[] = { INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT1, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT1_RSVD, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT2_RSVD, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_GT2_PLUS_RSVD, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT1, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, &intel_haswell_info ), @@ -286,6 +290,10 @@ static const struct pci_id_match intel_device_match[] = { INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT1, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT1_RSVD, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT2_RSVD, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_GT2_PLUS_RSVD, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT1, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, &intel_haswell_info ), @@ -295,6 +303,9 @@ static const struct pci_id_match intel_device_match[] = { INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT1, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT1_RSVD, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT2_RSVD, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_GT2_PLUS_RSVD, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT1, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, &intel_haswell_info ), @@ -304,6 +315,9 @@ static const struct pci_id_match intel_device_match[] = { INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT1, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT1_RSVD, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT2_RSVD, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_GT2_PLUS_RSVD, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_PO, &intel_valleyview_info ), INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_1, &intel_valleyview_info ), |