diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2010-10-07 12:45:02 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-10-07 13:26:07 +0100 |
| commit | 4083197a44d1a1a05d33654b3c7d6e96d7472fe7 (patch) | |
| tree | ec2e0390c5330bc07576b32e26ccd96d19727977 /src/intel_shadow.c | |
| parent | 1444ea35706992a1f094fe029e6a7d9eec0f93c6 (diff) | |
Include a chipset generation number to clarify device specific paths.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'src/intel_shadow.c')
| -rw-r--r-- | src/intel_shadow.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/intel_shadow.c b/src/intel_shadow.c index 37e4cd2d..c12febc4 100644 --- a/src/intel_shadow.c +++ b/src/intel_shadow.c @@ -108,7 +108,7 @@ void intel_shadow_blt(intel_screen_private *intel) int n; /* Can we trust the BLT? Otherwise do an uncached mmecy. */ - if (IS_I8XX(intel) || IS_GEN6(intel)) { + if (IS_GEN2(intel) || IS_GEN6(intel)) { intel_shadow_memcpy(intel); return; } @@ -120,7 +120,7 @@ void intel_shadow_blt(intel_screen_private *intel) blt |= (XY_SRC_COPY_BLT_WRITE_ALPHA | XY_SRC_COPY_BLT_WRITE_RGB); - if (IS_I965G(intel)) { + if (INTEL_INFO(intel)->gen >= 40) { if (intel->front_tiling) { dst_pitch >>= 2; blt |= XY_SRC_COPY_BLT_DST_TILED; |