diff options
| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2011-02-22 18:31:44 +0100 |
|---|---|---|
| committer | Owain G. Ainsworth <oga@openbsd.org> | 2011-05-29 23:17:07 +0100 |
| commit | 15f093148847f47b67c9be72c1c86173d4df5302 (patch) | |
| tree | c32f4d054c807063a04d5af6f6e8c768b3a7d7d9 /src/intel_uxa.c | |
| parent | 80f16404fa5a2abaa86563072e46f062becd991e (diff) | |
Fix relaxed tiling on gen2
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit d21d781466785c317131a8a57606925867265dc8)
Signed-off-by: Owain G. Ainsworth <oga@openbsd.org>
Diffstat (limited to 'src/intel_uxa.c')
| -rw-r--r-- | src/intel_uxa.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/src/intel_uxa.c b/src/intel_uxa.c index 7cfe6d66..d485e34b 100644 --- a/src/intel_uxa.c +++ b/src/intel_uxa.c @@ -196,12 +196,16 @@ intel_uxa_pixmap_compute_size(PixmapPtr pixmap, *tiling = I915_TILING_NONE; if (*tiling != I915_TILING_NONE) { - int aligned_h; + int aligned_h, tile_height; if (*tiling == I915_TILING_X) - aligned_h = ALIGN(h, 8); + tile_height = 8; else - aligned_h = ALIGN(h, 32); + tile_height = 32; + /* i8xx has a 2-row interleaved tile layout */ + if (IS_GEN2(intel)) + tile_height *= 2; + aligned_h = ALIGN(h, tile_height); *stride = intel_get_fence_pitch(intel, ALIGN(pitch, 512), |