diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2011-04-04 19:21:10 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2011-04-04 19:24:30 +0100 |
| commit | 6f104189bb9439ab0e05f04d4be020813eb04bf9 (patch) | |
| tree | c1c8040c6520dbc3a37c729a73a5619678d66057 /src/intel_uxa.c | |
| parent | 314439860e595c473d168c0cafb2b5b49b7fef30 (diff) | |
Take advantage of the kernel flush for dirty bo in the busy ioctl
Rather than just creating and submitting a batch that simply contains a
flush in order to periodically ensure that rendering reaches the
scanout, we can simply ask the kernel whether the scanout is busy. The
kernel will then submit a flush on our behalf if it is dirty, which
takes advantage of the kernel's dirty state tracking.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'src/intel_uxa.c')
| -rw-r--r-- | src/intel_uxa.c | 28 |
1 files changed, 16 insertions, 12 deletions
diff --git a/src/intel_uxa.c b/src/intel_uxa.c index 662bcc7e..24ef6fae 100644 --- a/src/intel_uxa.c +++ b/src/intel_uxa.c @@ -88,7 +88,7 @@ static void gen6_context_switch(intel_screen_private *intel, int new_mode) { - intel_batch_submit(intel->scrn, FALSE); + intel_batch_submit(intel->scrn); } static void @@ -136,7 +136,7 @@ intel_get_aperture_space(ScrnInfoPtr scrn, drm_intel_bo ** bo_table, bo_table[0] = intel->batch_bo; if (drm_intel_bufmgr_check_aperture_space(bo_table, num_bos) != 0) { - intel_batch_submit(scrn, FALSE); + intel_batch_submit(scrn); bo_table[0] = intel->batch_bo; if (drm_intel_bufmgr_check_aperture_space(bo_table, num_bos) != 0) { @@ -703,7 +703,7 @@ static Bool intel_uxa_prepare_access(PixmapPtr pixmap, uxa_access_t access) if (!list_is_empty(&priv->batch) && (access == UXA_ACCESS_RW || priv->batch_write)) - intel_batch_submit(scrn, FALSE); + intel_batch_submit(scrn); if (priv->tiling || bo->size <= intel->max_gtt_map_size) ret = drm_intel_gem_bo_map_gtt(bo); @@ -921,7 +921,7 @@ static Bool intel_uxa_get_image(PixmapPtr pixmap, FreeScratchGC(gc); - intel_batch_submit(xf86Screens[screen->myNum], FALSE); + intel_batch_submit(xf86Screens[screen->myNum]); x = y = 0; pixmap = scratch; @@ -935,20 +935,24 @@ static Bool intel_uxa_get_image(PixmapPtr pixmap, return ret; } +static void intel_flush_rendering(intel_screen_private *intel) +{ + drm_intel_bo_busy(intel->front_buffer); +} + void intel_uxa_block_handler(intel_screen_private *intel) { if (intel->shadow_damage && pixman_region_not_empty(DamageRegion(intel->shadow_damage))) { intel_shadow_blt(intel); - /* Emit a flush of the rendering cache, or on the 965 - * and beyond rendering results may not hit the - * framebuffer until significantly later. - */ - intel_batch_submit(intel->scrn, TRUE); - DamageEmpty(intel->shadow_damage); - } else - intel_batch_submit(intel->scrn, TRUE); + } + + /* Emit a flush of the rendering cache, or on the 965 + * and beyond rendering results may not hit the + * framebuffer until significantly later. + */ + intel_flush_rendering(intel); } static PixmapPtr |