diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2010-08-22 09:54:18 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-08-22 09:54:18 +0100 |
| commit | 42312bbd8c9cbadf0adc4556b76987857d105bd9 (patch) | |
| tree | 35c45972773ea7eb833f38f73aecea1230d64968 /src/intel_uxa.c | |
| parent | 7f86e5b5da88201e5443e26619c35a1a9745cf68 (diff) | |
Remove accel_pitch_alignment
This has to be 64 on all generations currently, so replace the variable
with a constant.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'src/intel_uxa.c')
| -rw-r--r-- | src/intel_uxa.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/intel_uxa.c b/src/intel_uxa.c index b51c4eb3..3f5383f6 100644 --- a/src/intel_uxa.c +++ b/src/intel_uxa.c @@ -142,7 +142,7 @@ intel_uxa_pixmap_compute_size(PixmapPtr pixmap, if (*tiling != I915_TILING_NONE) { /* First check whether tiling is necessary. */ pitch = (w * pixmap->drawable.bitsPerPixel + 7) / 8; - pitch = ALIGN(pitch, intel->accel_pixmap_pitch_alignment); + pitch = ALIGN(pitch, 64); size = pitch * ALIGN (h, 2); if (!IS_I965G(intel)) { /* Older hardware requires fences to be pot size @@ -199,7 +199,7 @@ intel_uxa_pixmap_compute_size(PixmapPtr pixmap, * subspan doesn't address an invalid page offset beyond the * end of the GTT. */ - *stride = ALIGN(pitch, intel->accel_pixmap_pitch_alignment); + *stride = ALIGN(pitch, 64); size = *stride * ALIGN(h, 2); } @@ -1109,12 +1109,10 @@ intel_limits_init(intel_screen_private *intel) */ if (IS_I965G(intel)) { intel->accel_pixmap_offset_alignment = 4 * 2; - intel->accel_pixmap_pitch_alignment = 64; intel->accel_max_x = 8192; intel->accel_max_y = 8192; } else { intel->accel_pixmap_offset_alignment = 4; - intel->accel_pixmap_pitch_alignment = 64; intel->accel_max_x = 2048; intel->accel_max_y = 2048; } |