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authorChris Wilson <chris@chris-wilson.co.uk>2013-07-30 17:38:23 +0100
committerChris Wilson <chris@chris-wilson.co.uk>2013-07-30 23:02:50 +0100
commit493763301e995d02cb838d14348da46dd26444af (patch)
tree7389f1f2b4db12a19787eac6cf1164fa7786c443 /src/sna/gen7_render.c
parentcdbc097796b24ab42b60c49d9885a35573c96a89 (diff)
sna: Allow CPU access to scanouts if WT cached
On Iris, we may store the framebuffer in the eLLC/LLC and mark it as being Write-Through cached. This means that we can treat it as being cached for read accesses (either by the GPU or CPU), but must be careful to still not write directly to the scanout with the CPU (only the GPU writes are cached and coherent with the display). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'src/sna/gen7_render.c')
-rw-r--r--src/sna/gen7_render.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/sna/gen7_render.c b/src/sna/gen7_render.c
index be379d84..f0566327 100644
--- a/src/sna/gen7_render.c
+++ b/src/sna/gen7_render.c
@@ -2133,7 +2133,7 @@ static int prefer_blt_bo(struct sna *sna, struct kgem_bo *bo)
if (bo->rq)
return RQ_IS_BLT(bo->rq) ? 1 : -1;
- return bo->tiling == I915_TILING_NONE || bo->scanout;
+ return bo->tiling == I915_TILING_NONE || (bo->scanout && !sna->kgem.has_wt);
}
inline static bool prefer_blt_ring(struct sna *sna,