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authorChris Wilson <chris@chris-wilson.co.uk>2012-12-11 15:30:54 +0000
committerChris Wilson <chris@chris-wilson.co.uk>2012-12-11 15:30:54 +0000
commit39d6c65f437d7877c1647b7ecf45e76daabc76a6 (patch)
tree374d0fe05e2cbe7693e52d6f449196033a8e1ccd /src/sna
parent162e9a2bfc693db186aa481551cf76b3dc5ee55c (diff)
sna/dri: Query current msc before use
Might be worth caching the last-known-value so we can skip the query for an old swap request. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'src/sna')
-rw-r--r--src/sna/sna_dri.c32
1 files changed, 15 insertions, 17 deletions
diff --git a/src/sna/sna_dri.c b/src/sna/sna_dri.c
index 83a00dd9..2e3cd122 100644
--- a/src/sna/sna_dri.c
+++ b/src/sna/sna_dri.c
@@ -1722,6 +1722,13 @@ sna_dri_schedule_flip(ClientPtr client, DrawablePtr draw, DRI2BufferPtr front,
return false;
}
+ /* Get current count */
+ vbl.request.type = DRM_VBLANK_RELATIVE | pipe_select(pipe);
+ vbl.request.sequence = 0;
+ if (sna_wait_vblank(sna, &vbl))
+ return false;
+ current_msc = vbl.reply.sequence;
+
/* Truncate to match kernel interfaces; means occasional overflow
* misses, but that's generally not a big deal */
divisor &= 0xffffffff;
@@ -1818,15 +1825,6 @@ sna_dri_schedule_flip(ClientPtr client, DrawablePtr draw, DRI2BufferPtr front,
sna_dri_reference_buffer(front);
sna_dri_reference_buffer(back);
- /* Get current count */
- vbl.request.type = DRM_VBLANK_RELATIVE | pipe_select(pipe);
- vbl.request.sequence = 0;
- if (sna_wait_vblank(sna, &vbl)) {
- sna_dri_frame_event_info_free(sna, draw, info);
- return false;
- }
-
- current_msc = vbl.reply.sequence;
*target_msc &= 0xffffffff;
remainder &= 0xffffffff;
@@ -2068,6 +2066,14 @@ sna_dri_schedule_swap(ClientPtr client, DrawablePtr draw, DRI2BufferPtr front,
sna_dri_reference_buffer(back);
info->type = swap_type;
+
+ /* Get current count */
+ vbl.request.type = DRM_VBLANK_RELATIVE | pipe_select(pipe);
+ vbl.request.sequence = 0;
+ if (sna_wait_vblank(sna, &vbl))
+ goto blit_fallback;
+ current_msc = vbl.reply.sequence;
+
if (divisor == 0 && current_msc <= *target_msc) {
if (can_exchange(sna, draw, front, back)) {
sna_dri_immediate_xchg(sna, draw, info);
@@ -2081,14 +2087,6 @@ sna_dri_schedule_swap(ClientPtr client, DrawablePtr draw, DRI2BufferPtr front,
return TRUE;
}
- /* Get current count */
- vbl.request.type = DRM_VBLANK_RELATIVE | pipe_select(pipe);
- vbl.request.sequence = 0;
- if (sna_wait_vblank(sna, &vbl))
- goto blit_fallback;
-
- current_msc = vbl.reply.sequence;
-
/*
* If divisor is zero, or current_msc is smaller than target_msc
* we just need to make sure target_msc passes before initiating