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authorZou Nan hai <nanhai.zou@intel.com>2008-11-27 10:48:09 +0800
committerZou Nan hai <nanhai.zou@intel.com>2008-11-27 10:48:09 +0800
commitec7fd3d1b477928f9bffde1a72d7f3fdea89e629 (patch)
tree3fb8388c6795b08c967a41689c658f2bde4398a8 /src/xvmc/read_field_x1y0_uv_igd.g4i
parentd978cd4b453ea588ed2fc2f2cb4ec26856fe00d4 (diff)
parentbaec75a56d91546443a2e04812face4997bc764b (diff)
Merge branch '965-xvmc'
Conflicts: src/common.h src/i830_hwmc.c src/i830_video.c
Diffstat (limited to 'src/xvmc/read_field_x1y0_uv_igd.g4i')
-rw-r--r--src/xvmc/read_field_x1y0_uv_igd.g4i40
1 files changed, 40 insertions, 0 deletions
diff --git a/src/xvmc/read_field_x1y0_uv_igd.g4i b/src/xvmc/read_field_x1y0_uv_igd.g4i
new file mode 100644
index 00000000..fc56acce
--- /dev/null
+++ b/src/xvmc/read_field_x1y0_uv_igd.g4i
@@ -0,0 +1,40 @@
+/*
+ * Copyright © 2008 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Author:
+ * Zou Nan hai <nanhai.zou@intel.com>
+ * Zhang Hua jun <huajun.zhang@intel.com>
+ * Xing Dong sheng <dongsheng.xing@intel.com>
+ *
+ */
+mov (1) g115.8<1>UD 0x07000FUD {align1}; // 8*16/32=4
+send (16) 0 g86.0<1>UW g115<16,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 4 {align1};//U
+send (16) 0 g91.0<1>UW g115<16,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 4 {align1};//V
+
+avg.sat (16) g78.0<1>UW g86.0<16,8,1>UB g86.1<16,8,1>UB {align1};
+avg.sat (16) g79.0<1>UW g87.0<16,8,1>UB g87.1<16,8,1>UB {align1};
+avg.sat (16) g80.0<1>UW g88.0<16,8,1>UB g88.1<16,8,1>UB {align1};
+avg.sat (16) g81.0<1>UW g89.0<16,8,1>UB g89.1<16,8,1>UB {align1};
+avg.sat (16) g82.0<1>UW g91.0<16,8,1>UB g91.1<16,8,1>UB {align1};
+avg.sat (16) g83.0<1>UW g92.0<16,8,1>UB g92.1<16,8,1>UB {align1};
+avg.sat (16) g84.0<1>UW g93.0<16,8,1>UB g93.1<16,8,1>UB {align1};
+avg.sat (16) g85.0<1>UW g94.0<16,8,1>UB g94.1<16,8,1>UB {align1};