diff options
| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2010-03-02 21:53:23 +0100 |
|---|---|---|
| committer | Carl Worth <cworth@cworth.org> | 2010-03-04 09:38:38 -0800 |
| commit | 9bba123c5f0f081562306c152e70221fc5041a3b (patch) | |
| tree | b981218281f727e5c1174b16d9872aeb38417d1e /src/xvmc | |
| parent | b11623f20e303ae1d90d4a6bf0d5d73970b4e9bf (diff) | |
i915 XvMC: drop superflous MI_FLUSH
Cache coherency is now fully under the control of gem.
For lack of hw documentation, I had to find out the correct cache
placements by trial and error:
Backward and forward surfaces: I915_GEM_DOMAIN_RENDER
Correlation data: I915_GEM_DOMAIN_SAMPLER
Changing any of them leads to visual corruptions, so I think these
are the correct ones.
Reviewed-by: Carl Worth <cworth@cworth.org>
Diffstat (limited to 'src/xvmc')
| -rw-r--r-- | src/xvmc/i915_structs.h | 18 | ||||
| -rw-r--r-- | src/xvmc/i915_xvmc.c | 14 |
2 files changed, 0 insertions, 32 deletions
diff --git a/src/xvmc/i915_structs.h b/src/xvmc/i915_structs.h index 7281fe58..2aa9d239 100644 --- a/src/xvmc/i915_structs.h +++ b/src/xvmc/i915_structs.h @@ -30,24 +30,6 @@ #include <stdint.h> -/* MI_INSTRUCTION */ -#define CMD_MI 0x00 - -#define OPC_MI_FLUSH (0x04) - -struct i915_mi_flush { - struct { - unsigned map_cache_invalidate:1; - unsigned pad0:1; - unsigned render_cache_flush_inhibit:1; - unsigned scene_count:1; - unsigned end_scene:1; - unsigned pad1:18; - unsigned opcode:6; - unsigned type:3; - } dw0; -}; - /* BLT */ #define CMD_2D 0x02 #define OPC_COLOR_BLT (0x40) diff --git a/src/xvmc/i915_xvmc.c b/src/xvmc/i915_xvmc.c index cda8c752..6a156d04 100644 --- a/src/xvmc/i915_xvmc.c +++ b/src/xvmc/i915_xvmc.c @@ -679,19 +679,6 @@ static void i915_mc_map_state_set(XvMCContext * context, drm_intel_gem_bo_unmap_gtt(pI915XvMC->msb_bo); } -static void i915_flush(int map, int render) -{ - struct i915_mi_flush mi_flush; - - memset(&mi_flush, 0, sizeof(mi_flush)); - mi_flush.dw0.type = CMD_MI; - mi_flush.dw0.opcode = OPC_MI_FLUSH; - mi_flush.dw0.map_cache_invalidate = map; - mi_flush.dw0.render_cache_flush_inhibit = render; - - intelBatchbufferData(&mi_flush, sizeof(mi_flush), 0); -} - static void i915_mc_load_indirect_render_emit(XvMCContext * context) { i915XvMCContext *pI915XvMC = (i915XvMCContext *) context->privData; @@ -1250,7 +1237,6 @@ static int i915_xvmc_mc_render_surface(Display * display, XvMCContext * context, drm_intel_gem_bo_unmap_gtt(pI915XvMC->corrdata_bo); - i915_flush(1, 0); // i915_mc_invalidate_subcontext_buffers(context, BLOCK_SIS | BLOCK_DIS | BLOCK_SSB // | BLOCK_MSB | BLOCK_PSP | BLOCK_PSC); |