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authorEric Anholt <eric@anholt.net>2009-10-06 18:02:38 -0700
committerEric Anholt <eric@anholt.net>2009-10-08 15:34:09 -0700
commitcc5d3ba3c331c3b1becf2d19277b24144bf34cfa (patch)
tree7c202c42fc4915c806086de18db4a76b9003ed5c /src
parent03e8e64f8669263e3cecb79ea57d5a26c0eaee3f (diff)
Rename the screen private from I830Ptr pI830 to intel_screen_private *intel.
This is the beginning of the campaign to remove some of the absurd use of Hungarian in the driver. Not that I don't like Hungarian, but I don't need to know that pI830 is a pPointer.
Diffstat (limited to 'src')
-rw-r--r--src/common.h4
-rw-r--r--src/drmmode_display.c36
-rw-r--r--src/i830.h24
-rw-r--r--src/i830_3d.c2
-rw-r--r--src/i830_accel.c28
-rw-r--r--src/i830_batchbuffer.c82
-rw-r--r--src/i830_batchbuffer.h94
-rw-r--r--src/i830_bios.c64
-rw-r--r--src/i830_dri.c32
-rw-r--r--src/i830_driver.c348
-rw-r--r--src/i830_hwmc.c34
-rw-r--r--src/i830_memory.c138
-rw-r--r--src/i830_render.c180
-rw-r--r--src/i830_ring.h54
-rw-r--r--src/i830_uxa.c156
-rw-r--r--src/i830_video.c106
-rw-r--r--src/i830_video.h4
-rw-r--r--src/i915_3d.c2
-rw-r--r--src/i915_hwmc.c74
-rw-r--r--src/i915_render.c210
-rw-r--r--src/i915_video.c12
-rw-r--r--src/i965_hwmc.c14
-rw-r--r--src/i965_render.c174
-rw-r--r--src/i965_video.c196
24 files changed, 1035 insertions, 1033 deletions
diff --git a/src/common.h b/src/common.h
index e509a715..505fcb2b 100644
--- a/src/common.h
+++ b/src/common.h
@@ -89,7 +89,7 @@ extern void I830DPRINTF_stub(const char *filename, int line,
#ifdef _I830_H_
#define PrintErrorState i830_dump_error_state
#define WaitRingFunc I830WaitLpRing
-#define RecPtr pI830
+#define RecPtr intel
#else
#define PrintErrorState I810PrintErrorState
#define WaitRingFunc I810WaitLpRing
@@ -373,7 +373,7 @@ extern int I810_DEBUG;
/* dsparb controlled by hw only */
#define DSPARB_HWCONTROL(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810))
/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */
-#define SUPPORTS_YTILING(pI810) (IS_I965G(pI830))
+#define SUPPORTS_YTILING(pI810) (IS_I965G(intel))
#define GTT_PAGE_SIZE KB(4)
#define ROUND_TO(x, y) (((x) + (y) - 1) / (y) * (y))
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 00b17dcb..7358cad7 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -299,7 +299,7 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode,
Rotation rotation, int x, int y)
{
ScrnInfoPtr pScrn = crtc->scrn;
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn);
drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
drmmode_ptr drmmode = drmmode_crtc->drmmode;
@@ -312,13 +312,13 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode,
int i;
int fb_id;
drmModeModeInfo kmode;
- unsigned int pitch = pScrn->displayWidth * pI830->cpp;
+ unsigned int pitch = pScrn->displayWidth * intel->cpp;
if (drmmode->fb_id == 0) {
ret = drmModeAddFB(drmmode->fd,
pScrn->virtualX, pScrn->virtualY,
pScrn->depth, pScrn->bitsPerPixel,
- pitch, pI830->front_buffer->bo->handle,
+ pitch, intel->front_buffer->bo->handle,
&drmmode->fb_id);
if (ret < 0) {
ErrorF("failed to add fb\n");
@@ -459,7 +459,7 @@ static void *
drmmode_crtc_shadow_allocate(xf86CrtcPtr crtc, int width, int height)
{
ScrnInfoPtr pScrn = crtc->scrn;
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
drmmode_ptr drmmode = drmmode_crtc->drmmode;
int size, ret;
@@ -470,7 +470,7 @@ drmmode_crtc_shadow_allocate(xf86CrtcPtr crtc, int width, int height)
size = rotate_pitch * height;
drmmode_crtc->rotate_bo =
- drm_intel_bo_alloc(pI830->bufmgr, "rotate", size, 4096);
+ drm_intel_bo_alloc(intel->bufmgr, "rotate", size, 4096);
if (!drmmode_crtc->rotate_bo) {
xf86DrvMsg(crtc->scrn->scrnIndex, X_ERROR,
@@ -1300,7 +1300,7 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
drmmode_crtc_private_ptr
drmmode_crtc = xf86_config->crtc[0]->driver_private;
drmmode_ptr drmmode = drmmode_crtc->drmmode;
- I830Ptr pI830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
i830_memory *old_front = NULL;
Bool tiled, ret;
ScreenPtr screen = screenInfo.screens[scrn->scrnIndex];
@@ -1310,8 +1310,8 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
if (scrn->virtualX == width && scrn->virtualY == height)
return TRUE;
- pitch = i830_pad_drawable_width(width, pI830->cpp);
- tiled = i830_tiled_width(pI830, &pitch, pI830->cpp);
+ pitch = i830_pad_drawable_width(width, intel->cpp);
+ tiled = i830_tiled_width(intel, &pitch, intel->cpp);
xf86DrvMsg(scrn->scrnIndex, X_INFO,
"Allocate new frame buffer %dx%d stride %d\n",
width, height, pitch);
@@ -1320,26 +1320,26 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
old_height = scrn->virtualY;
old_pitch = scrn->displayWidth;
old_fb_id = drmmode->fb_id;
- old_front = pI830->front_buffer;
+ old_front = intel->front_buffer;
scrn->virtualX = width;
scrn->virtualY = height;
scrn->displayWidth = pitch;
- pI830->front_buffer = i830_allocate_framebuffer(scrn);
- if (!pI830->front_buffer)
+ intel->front_buffer = i830_allocate_framebuffer(scrn);
+ if (!intel->front_buffer)
goto fail;
ret = drmModeAddFB(drmmode->fd, width, height, scrn->depth,
- scrn->bitsPerPixel, pitch * pI830->cpp,
- pI830->front_buffer->bo->handle,
+ scrn->bitsPerPixel, pitch * intel->cpp,
+ intel->front_buffer->bo->handle,
&drmmode->fb_id);
if (ret)
goto fail;
- i830_set_pixmap_bo(screen->GetScreenPixmap(screen), pI830->front_buffer->bo);
+ i830_set_pixmap_bo(screen->GetScreenPixmap(screen), intel->front_buffer->bo);
screen->ModifyPixmapHeader(screen->GetScreenPixmap(screen),
- width, height, -1, -1, pitch * pI830->cpp, NULL);
+ width, height, -1, -1, pitch * intel->cpp, NULL);
for (i = 0; i < xf86_config->num_crtc; i++) {
xf86CrtcPtr crtc = xf86_config->crtc[i];
@@ -1359,9 +1359,9 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
return TRUE;
fail:
- if (pI830->front_buffer)
- i830_free_memory(scrn, pI830->front_buffer);
- pI830->front_buffer = old_front;
+ if (intel->front_buffer)
+ i830_free_memory(scrn, intel->front_buffer);
+ intel->front_buffer = old_front;
scrn->virtualX = old_width;
scrn->virtualY = old_height;
scrn->displayWidth = old_pitch;
diff --git a/src/i830.h b/src/i830.h
index 9719651d..e6eb4b97 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -93,8 +93,6 @@ typedef struct _I830OutputRec I830OutputRec, *I830OutputPtr;
#define ALWAYS_SYNC 0
#define ALWAYS_FLUSH 0
-typedef struct _I830Rec *I830Ptr;
-
enum tile_format {
TILE_NONE,
TILE_XMAJOR,
@@ -166,7 +164,7 @@ enum dri_type {
DRI_DRI2
};
-typedef struct _I830Rec {
+typedef struct intel_screen_private {
unsigned char *MMIOBase;
int cpp;
@@ -305,9 +303,13 @@ typedef struct _I830Rec {
* User option to print acceleration fallback info to the server log.
*/
Bool fallback_debug;
-} I830Rec;
+} intel_screen_private;
-#define I830PTR(p) ((I830Ptr)((p)->driverPrivate))
+static inline intel_screen_private *
+intel_get_screen_private(ScrnInfoPtr scrn)
+{
+ return (intel_screen_private *)(scrn->driverPrivate);
+}
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
#define ALIGN(i,m) (((i) + (m) - 1) & ~((m) - 1))
@@ -367,14 +369,14 @@ Bool i830_allocate_xvmc_buffer(ScrnInfoPtr pScrn, const char *name,
void i830_free_xvmc_buffer(ScrnInfoPtr pScrn, i830_memory * buffer);
#endif
-Bool i830_tiled_width(I830Ptr i830, int *width, int cpp);
+Bool i830_tiled_width(intel_screen_private *intel, int *width, int cpp);
int i830_pad_drawable_width(int width, int cpp);
/* i830_memory.c */
Bool i830_bind_all_memory(ScrnInfoPtr pScrn);
-unsigned long i830_get_fence_size(I830Ptr pI830, unsigned long size);
-unsigned long i830_get_fence_pitch(I830Ptr pI830, unsigned long pitch,
+unsigned long i830_get_fence_size(intel_screen_private *intel, unsigned long size);
+unsigned long i830_get_fence_pitch(intel_screen_private *intel, unsigned long pitch,
int format);
void i830_set_max_gtt_map_size(ScrnInfoPtr pScrn);
@@ -427,7 +429,7 @@ void i830_enter_render(ScrnInfoPtr);
#define I830FALLBACK(s, arg...) \
do { \
- if (I830PTR(pScrn)->fallback_debug) { \
+ if (intel_get_screen_private(pScrn)->fallback_debug) { \
xf86DrvMsg(pScrn->scrnIndex, X_INFO, \
"fallback: " s "\n", ##arg); \
} \
@@ -469,10 +471,10 @@ static inline drm_intel_bo *intel_bo_alloc_for_data(ScrnInfoPtr scrn,
unsigned int size,
char *name)
{
- I830Ptr pI830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
drm_intel_bo *bo;
- bo = drm_intel_bo_alloc(pI830->bufmgr, name, size, 4096);
+ bo = drm_intel_bo_alloc(intel->bufmgr, name, size, 4096);
if (!bo)
return NULL;
drm_intel_bo_subdata(bo, 0, size, data);
diff --git a/src/i830_3d.c b/src/i830_3d.c
index 871b45b2..28527dcc 100644
--- a/src/i830_3d.c
+++ b/src/i830_3d.c
@@ -36,7 +36,7 @@
void I830EmitInvarientState(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
BEGIN_BATCH(58);
diff --git a/src/i830_accel.c b/src/i830_accel.c
index 51aa6a4a..f9cbda8f 100644
--- a/src/i830_accel.c
+++ b/src/i830_accel.c
@@ -55,12 +55,12 @@ unsigned long intel_get_pixmap_pitch(PixmapPtr pPix)
void I830Sync(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
if (I810_DEBUG & (DEBUG_VERBOSE_ACCEL | DEBUG_VERBOSE_SYNC))
ErrorF("I830Sync\n");
- if (!pScrn->vtSema || !pI830->batch_bo)
+ if (!pScrn->vtSema || !intel->batch_bo)
return;
I830EmitFlush(pScrn);
@@ -71,10 +71,10 @@ void I830Sync(ScrnInfoPtr pScrn)
void I830EmitFlush(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
- if (IS_I965G(pI830))
+ if (IS_I965G(intel))
flags = 0;
{
@@ -101,7 +101,7 @@ void i830_debug_sync(ScrnInfoPtr scrn)
Bool I830AccelInit(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
/* Limits are described in the BLT engine chapter under Graphics Data Size
* Limitations, and the descriptions of SURFACE_STATE, 3DSTATE_BUFFER_INFO,
@@ -141,16 +141,16 @@ Bool I830AccelInit(ScreenPtr pScreen)
* the front, which will have an appropriate pitch/offset already set up,
* so UXA doesn't need to worry.
*/
- if (IS_I965G(pI830)) {
- pI830->accel_pixmap_offset_alignment = 4 * 2;
- pI830->accel_pixmap_pitch_alignment = 64;
- pI830->accel_max_x = 8192;
- pI830->accel_max_y = 8192;
+ if (IS_I965G(intel)) {
+ intel->accel_pixmap_offset_alignment = 4 * 2;
+ intel->accel_pixmap_pitch_alignment = 64;
+ intel->accel_max_x = 8192;
+ intel->accel_max_y = 8192;
} else {
- pI830->accel_pixmap_offset_alignment = 4;
- pI830->accel_pixmap_pitch_alignment = 64;
- pI830->accel_max_x = 2048;
- pI830->accel_max_y = 2048;
+ intel->accel_pixmap_offset_alignment = 4;
+ intel->accel_pixmap_pitch_alignment = 64;
+ intel->accel_max_x = 2048;
+ intel->accel_max_y = 2048;
}
return i830_uxa_init(pScreen);
diff --git a/src/i830_batchbuffer.c b/src/i830_batchbuffer.c
index 48a2e1e9..553eeb3b 100644
--- a/src/i830_batchbuffer.c
+++ b/src/i830_batchbuffer.c
@@ -41,79 +41,79 @@
static void intel_next_batch(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
/* The 865 has issues with larger-than-page-sized batch buffers. */
- if (IS_I865G(pI830))
- pI830->batch_bo =
- dri_bo_alloc(pI830->bufmgr, "batch", 4096, 4096);
+ if (IS_I865G(intel))
+ intel->batch_bo =
+ dri_bo_alloc(intel->bufmgr, "batch", 4096, 4096);
else
- pI830->batch_bo =
- dri_bo_alloc(pI830->bufmgr, "batch", 4096 * 4, 4096);
+ intel->batch_bo =
+ dri_bo_alloc(intel->bufmgr, "batch", 4096 * 4, 4096);
- if (dri_bo_map(pI830->batch_bo, 1) != 0)
+ if (dri_bo_map(intel->batch_bo, 1) != 0)
FatalError("Failed to map batchbuffer: %s\n", strerror(errno));
- pI830->batch_used = 0;
- pI830->batch_ptr = pI830->batch_bo->virtual;
+ intel->batch_used = 0;
+ intel->batch_ptr = intel->batch_bo->virtual;
/* If we are using DRI2, we don't know when another client has executed,
* so we have to reinitialize our 3D state per batch.
*/
- if (pI830->directRenderingType == DRI_DRI2)
- pI830->last_3d = LAST_3D_OTHER;
+ if (intel->directRenderingType == DRI_DRI2)
+ intel->last_3d = LAST_3D_OTHER;
}
void intel_batch_init(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
- pI830->batch_emit_start = 0;
- pI830->batch_emitting = 0;
+ intel->batch_emit_start = 0;
+ intel->batch_emitting = 0;
intel_next_batch(pScrn);
}
void intel_batch_teardown(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
- if (pI830->batch_ptr != NULL) {
- dri_bo_unmap(pI830->batch_bo);
- pI830->batch_ptr = NULL;
+ if (intel->batch_ptr != NULL) {
+ dri_bo_unmap(intel->batch_bo);
+ intel->batch_ptr = NULL;
- dri_bo_unreference(pI830->batch_bo);
- pI830->batch_bo = NULL;
+ dri_bo_unreference(intel->batch_bo);
+ intel->batch_bo = NULL;
- dri_bo_unreference(pI830->last_batch_bo);
- pI830->last_batch_bo = NULL;
+ dri_bo_unreference(intel->last_batch_bo);
+ intel->last_batch_bo = NULL;
}
}
void intel_batch_flush(ScrnInfoPtr pScrn, Bool flushed)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
int ret;
- if (pI830->batch_used == 0)
+ if (intel->batch_used == 0)
return;
/* Emit a padding dword if we aren't going to be quad-word aligned. */
- if ((pI830->batch_used & 4) == 0) {
- *(uint32_t *) (pI830->batch_ptr + pI830->batch_used) = MI_NOOP;
- pI830->batch_used += 4;
+ if ((intel->batch_used & 4) == 0) {
+ *(uint32_t *) (intel->batch_ptr + intel->batch_used) = MI_NOOP;
+ intel->batch_used += 4;
}
/* Mark the end of the batchbuffer. */
- *(uint32_t *) (pI830->batch_ptr + pI830->batch_used) =
+ *(uint32_t *) (intel->batch_ptr + intel->batch_used) =
MI_BATCH_BUFFER_END;
- pI830->batch_used += 4;
+ intel->batch_used += 4;
- dri_bo_unmap(pI830->batch_bo);
- pI830->batch_ptr = NULL;
+ dri_bo_unmap(intel->batch_bo);
+ intel->batch_ptr = NULL;
ret =
- dri_bo_exec(pI830->batch_bo, pI830->batch_used, NULL, 0,
+ dri_bo_exec(intel->batch_bo, intel->batch_used, NULL, 0,
0xffffffff);
if (ret != 0)
FatalError("Failed to submit batchbuffer: %s\n",
@@ -122,9 +122,9 @@ void intel_batch_flush(ScrnInfoPtr pScrn, Bool flushed)
/* Save a ref to the last batch emitted, which we use for syncing
* in debug code.
*/
- dri_bo_unreference(pI830->last_batch_bo);
- pI830->last_batch_bo = pI830->batch_bo;
- pI830->batch_bo = NULL;
+ dri_bo_unreference(intel->last_batch_bo);
+ intel->last_batch_bo = intel->batch_bo;
+ intel->batch_bo = NULL;
intel_next_batch(pScrn);
@@ -132,20 +132,20 @@ void intel_batch_flush(ScrnInfoPtr pScrn, Bool flushed)
* blockhandler. We could set this less often, but it's probably not worth
* the work.
*/
- pI830->need_mi_flush = TRUE;
+ intel->need_mi_flush = TRUE;
- if (pI830->batch_flush_notify)
- pI830->batch_flush_notify(pScrn);
+ if (intel->batch_flush_notify)
+ intel->batch_flush_notify(pScrn);
}
/** Waits on the last emitted batchbuffer to be completed. */
void intel_batch_wait_last(ScrnInfoPtr scrn)
{
- I830Ptr pI830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
/* Map it CPU write, which guarantees it's done. This is a completely
* non performance path, so we don't need anything better.
*/
- drm_intel_bo_map(pI830->last_batch_bo, TRUE);
- drm_intel_bo_unmap(pI830->last_batch_bo);
+ drm_intel_bo_map(intel->last_batch_bo, TRUE);
+ drm_intel_bo_unmap(intel->last_batch_bo);
}
diff --git a/src/i830_batchbuffer.h b/src/i830_batchbuffer.h
index a00a4364..cd8e0265 100644
--- a/src/i830_batchbuffer.h
+++ b/src/i830_batchbuffer.h
@@ -37,79 +37,79 @@ void intel_batch_teardown(ScrnInfoPtr pScrn);
void intel_batch_flush(ScrnInfoPtr pScrn, Bool flushed);
void intel_batch_wait_last(ScrnInfoPtr pScrn);
-static inline int intel_batch_space(I830Ptr pI830)
+static inline int intel_batch_space(intel_screen_private *intel)
{
- return (pI830->batch_bo->size - BATCH_RESERVED) - (pI830->batch_used);
+ return (intel->batch_bo->size - BATCH_RESERVED) - (intel->batch_used);
}
static inline void
-intel_batch_require_space(ScrnInfoPtr pScrn, I830Ptr pI830, GLuint sz)
+intel_batch_require_space(ScrnInfoPtr pScrn, intel_screen_private *intel, GLuint sz)
{
- assert(sz < pI830->batch_bo->size - 8);
- if (intel_batch_space(pI830) < sz)
+ assert(sz < intel->batch_bo->size - 8);
+ if (intel_batch_space(intel) < sz)
intel_batch_flush(pScrn, FALSE);
}
static inline void intel_batch_start_atomic(ScrnInfoPtr pScrn, unsigned int sz)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
- assert(!pI830->in_batch_atomic);
- intel_batch_require_space(pScrn, pI830, sz * 4);
+ assert(!intel->in_batch_atomic);
+ intel_batch_require_space(pScrn, intel, sz * 4);
- pI830->in_batch_atomic = TRUE;
- pI830->batch_atomic_limit = pI830->batch_used + sz * 4;
+ intel->in_batch_atomic = TRUE;
+ intel->batch_atomic_limit = intel->batch_used + sz * 4;
}
static inline void intel_batch_end_atomic(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
- assert(pI830->in_batch_atomic);
- assert(pI830->batch_used <= pI830->batch_atomic_limit);
- pI830->in_batch_atomic = FALSE;
+ assert(intel->in_batch_atomic);
+ assert(intel->batch_used <= intel->batch_atomic_limit);
+ intel->in_batch_atomic = FALSE;
}
-static inline void intel_batch_emit_dword(I830Ptr pI830, uint32_t dword)
+static inline void intel_batch_emit_dword(intel_screen_private *intel, uint32_t dword)
{
- assert(pI830->batch_ptr != NULL);
- assert(intel_batch_space(pI830) >= 4);
- *(uint32_t *) (pI830->batch_ptr + pI830->batch_used) = dword;
- pI830->batch_used += 4;
+ assert(intel->batch_ptr != NULL);
+ assert(intel_batch_space(intel) >= 4);
+ *(uint32_t *) (intel->batch_ptr + intel->batch_used) = dword;
+ intel->batch_used += 4;
}
static inline void
-intel_batch_emit_reloc(I830Ptr pI830,
+intel_batch_emit_reloc(intel_screen_private *intel,
dri_bo * bo,
uint32_t read_domains,
uint32_t write_domains, uint32_t delta)
{
- assert(intel_batch_space(pI830) >= 4);
- *(uint32_t *) (pI830->batch_ptr + pI830->batch_used) =
+ assert(intel_batch_space(intel) >= 4);
+ *(uint32_t *) (intel->batch_ptr + intel->batch_used) =
bo->offset + delta;
- dri_bo_emit_reloc(pI830->batch_bo, read_domains, write_domains, delta,
- pI830->batch_used, bo);
- pI830->batch_used += 4;
+ dri_bo_emit_reloc(intel->batch_bo, read_domains, write_domains, delta,
+ intel->batch_used, bo);
+ intel->batch_used += 4;
}
static inline void
-intel_batch_emit_reloc_pixmap(I830Ptr pI830, PixmapPtr pPixmap,
+intel_batch_emit_reloc_pixmap(intel_screen_private *intel, PixmapPtr pPixmap,
uint32_t read_domains, uint32_t write_domain,
uint32_t delta)
{
dri_bo *bo = i830_get_pixmap_bo(pPixmap);
- assert(pI830->batch_ptr != NULL);
- assert(intel_batch_space(pI830) >= 4);
- intel_batch_emit_reloc(pI830, bo, read_domains, write_domain, delta);
+ assert(intel->batch_ptr != NULL);
+ assert(intel_batch_space(intel) >= 4);
+ intel_batch_emit_reloc(intel, bo, read_domains, write_domain, delta);
}
-#define OUT_BATCH(dword) intel_batch_emit_dword(pI830, dword)
+#define OUT_BATCH(dword) intel_batch_emit_dword(intel, dword)
#define OUT_RELOC(bo, read_domains, write_domains, delta) \
- intel_batch_emit_reloc (pI830, bo, read_domains, write_domains, delta)
+ intel_batch_emit_reloc (intel, bo, read_domains, write_domains, delta)
#define OUT_RELOC_PIXMAP(pPixmap, reads, write, delta) \
- intel_batch_emit_reloc_pixmap(pI830, pPixmap, reads, write, delta)
+ intel_batch_emit_reloc_pixmap(intel, pPixmap, reads, write, delta)
union intfloat {
float f;
@@ -124,36 +124,36 @@ union intfloat {
#define BEGIN_BATCH(n) \
do { \
- if (pI830->batch_emitting != 0) \
+ if (intel->batch_emitting != 0) \
FatalError("%s: BEGIN_BATCH called without closing " \
"ADVANCE_BATCH\n", __FUNCTION__); \
- intel_batch_require_space(pScrn, pI830, (n) * 4); \
- pI830->batch_emitting = (n) * 4; \
- pI830->batch_emit_start = pI830->batch_used; \
+ intel_batch_require_space(pScrn, intel, (n) * 4); \
+ intel->batch_emitting = (n) * 4; \
+ intel->batch_emit_start = intel->batch_used; \
} while (0)
#define ADVANCE_BATCH() do { \
- if (pI830->batch_emitting == 0) \
+ if (intel->batch_emitting == 0) \
FatalError("%s: ADVANCE_BATCH called with no matching " \
"BEGIN_BATCH\n", __FUNCTION__); \
- if (pI830->batch_used > \
- pI830->batch_emit_start + pI830->batch_emitting) \
+ if (intel->batch_used > \
+ intel->batch_emit_start + intel->batch_emitting) \
FatalError("%s: ADVANCE_BATCH: exceeded allocation %d/%d\n ", \
__FUNCTION__, \
- pI830->batch_used - pI830->batch_emit_start, \
- pI830->batch_emitting); \
- if (pI830->batch_used < pI830->batch_emit_start + \
- pI830->batch_emitting) \
+ intel->batch_used - intel->batch_emit_start, \
+ intel->batch_emitting); \
+ if (intel->batch_used < intel->batch_emit_start + \
+ intel->batch_emitting) \
FatalError("%s: ADVANCE_BATCH: under-used allocation %d/%d\n ", \
__FUNCTION__, \
- pI830->batch_used - pI830->batch_emit_start, \
- pI830->batch_emitting); \
- if ((pI830->batch_emitting > 8) && \
+ intel->batch_used - intel->batch_emit_start, \
+ intel->batch_emitting); \
+ if ((intel->batch_emitting > 8) && \
(I810_DEBUG & DEBUG_ALWAYS_SYNC)) { \
/* Note: not actually syncing, just flushing each batch. */ \
intel_batch_flush(pScrn, FALSE); \
} \
- pI830->batch_emitting = 0; \
+ intel->batch_emitting = 0; \
} while (0)
#endif /* _INTEL_BATCHBUFFER_H */
diff --git a/src/i830_bios.c b/src/i830_bios.c
index b8439407..f1f1644a 100644
--- a/src/i830_bios.c
+++ b/src/i830_bios.c
@@ -108,7 +108,7 @@ fill_detail_timing_data(DisplayModePtr fixed_mode, unsigned char *timing_ptr)
* offsets, such that this parsing fails. Thus, almost any other method for
* detecting the panel mode is preferable.
*/
-static void parse_integrated_panel_data(I830Ptr pI830, struct bdb_header *bdb)
+static void parse_integrated_panel_data(intel_screen_private *intel, struct bdb_header *bdb)
{
struct bdb_lvds_options *lvds_options;
struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs;
@@ -120,13 +120,13 @@ static void parse_integrated_panel_data(I830Ptr pI830, struct bdb_header *bdb)
int dvo_offset;
/* Defaults if we can't find VBT info */
- pI830->lvds_dither = 0;
+ intel->lvds_dither = 0;
lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
if (!lvds_options)
return;
- pI830->lvds_dither = lvds_options->pixel_dither;
+ intel->lvds_dither = lvds_options->pixel_dither;
if (lvds_options->panel_type == 0xff)
return;
@@ -147,7 +147,7 @@ static void parse_integrated_panel_data(I830Ptr pI830, struct bdb_header *bdb)
(lfp_data_size *
lvds_options->panel_type));
timing_ptr = (unsigned char *)entry + dvo_offset;
- if (pI830->skip_panel_detect)
+ if (intel->skip_panel_detect)
return;
fixed_mode = xnfalloc(sizeof(DisplayModeRec));
@@ -157,16 +157,16 @@ static void parse_integrated_panel_data(I830Ptr pI830, struct bdb_header *bdb)
* block, pull the contents out using EDID macros.
*/
fill_detail_timing_data(fixed_mode, timing_ptr);
- pI830->lvds_fixed_mode = fixed_mode;
+ intel->lvds_fixed_mode = fixed_mode;
}
-static void parse_sdvo_panel_data(I830Ptr pI830, struct bdb_header *bdb)
+static void parse_sdvo_panel_data(intel_screen_private *intel, struct bdb_header *bdb)
{
DisplayModePtr fixed_mode;
struct bdb_sdvo_lvds_options *sdvo_lvds_options;
unsigned char *timing_ptr;
- pI830->sdvo_lvds_fixed_mode = NULL;
+ intel->sdvo_lvds_fixed_mode = NULL;
sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS);
if (sdvo_lvds_options == NULL)
@@ -184,47 +184,47 @@ static void parse_sdvo_panel_data(I830Ptr pI830, struct bdb_header *bdb)
fill_detail_timing_data(fixed_mode, timing_ptr +
(sdvo_lvds_options->panel_type *
DET_TIMING_INFO_LEN));
- pI830->sdvo_lvds_fixed_mode = fixed_mode;
+ intel->sdvo_lvds_fixed_mode = fixed_mode;
}
-static void parse_panel_data(I830Ptr pI830, struct bdb_header *bdb)
+static void parse_panel_data(intel_screen_private *intel, struct bdb_header *bdb)
{
- parse_integrated_panel_data(pI830, bdb);
- parse_sdvo_panel_data(pI830, bdb);
+ parse_integrated_panel_data(intel, bdb);
+ parse_sdvo_panel_data(intel, bdb);
}
-static void parse_general_features(I830Ptr pI830, struct bdb_header *bdb)
+static void parse_general_features(intel_screen_private *intel, struct bdb_header *bdb)
{
struct bdb_general_features *general;
/* Set sensible defaults in case we can't find the general block */
- pI830->tv_present = 1;
+ intel->tv_present = 1;
general = find_section(bdb, BDB_GENERAL_FEATURES);
if (!general)
return;
- pI830->tv_present = general->int_tv_support;
- pI830->lvds_use_ssc = general->enable_ssc;
- if (pI830->lvds_use_ssc) {
- if (IS_I85X(pI830))
- pI830->lvds_ssc_freq = general->ssc_freq ? 66 : 48;
+ intel->tv_present = general->int_tv_support;
+ intel->lvds_use_ssc = general->enable_ssc;
+ if (intel->lvds_use_ssc) {
+ if (IS_I85X(intel))
+ intel->lvds_ssc_freq = general->ssc_freq ? 66 : 48;
else
- pI830->lvds_ssc_freq = general->ssc_freq ? 100 : 96;
+ intel->lvds_ssc_freq = general->ssc_freq ? 100 : 96;
}
}
-static void parse_driver_feature(I830Ptr pI830, struct bdb_header *bdb)
+static void parse_driver_feature(intel_screen_private *intel, struct bdb_header *bdb)
{
struct bdb_driver_feature *feature;
/* For mobile chip, set default as true */
- if (IS_MOBILE(pI830) && !IS_I830(pI830))
- pI830->integrated_lvds = TRUE;
+ if (IS_MOBILE(intel) && !IS_I830(intel))
+ intel->integrated_lvds = TRUE;
/* skip pre-9xx chips which is broken to parse this block. */
- if (!IS_I9XX(pI830))
+ if (!IS_I9XX(intel))
return;
/* XXX Disable this parsing, as it looks doesn't work for all
@@ -238,7 +238,7 @@ static void parse_driver_feature(I830Ptr pI830, struct bdb_header *bdb)
return;
if (feature->lvds_config != BDB_DRIVER_INT_LVDS)
- pI830->integrated_lvds = FALSE;
+ intel->integrated_lvds = FALSE;
}
static
@@ -250,7 +250,7 @@ void parse_sdvo_mapping(ScrnInfoPtr pScrn, struct bdb_header *bdb)
struct child_device_config *child;
int i, child_device_num, count;
struct sdvo_device_mapping *p_mapping;
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
if (!defs) {
@@ -285,7 +285,7 @@ void parse_sdvo_mapping(ScrnInfoPtr pScrn, struct bdb_header *bdb)
child->slave_addr, child->dvo_port);
/* fill the primary dvo port */
p_mapping =
- &(pI830->sdvo_mappings[child->dvo_port - 1]);
+ &(intel->sdvo_mappings[child->dvo_port - 1]);
if (!p_mapping->initialized) {
p_mapping->dvo_port = child->dvo_port;
p_mapping->dvo_wiring = child->dvo_wiring;
@@ -335,7 +335,7 @@ void parse_sdvo_mapping(ScrnInfoPtr pScrn, struct bdb_header *bdb)
*/
int i830_bios_init(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
struct vbt_header *vbt;
struct bdb_header *bdb;
int vbt_off, bdb_off;
@@ -343,7 +343,7 @@ int i830_bios_init(ScrnInfoPtr pScrn)
int ret;
int size;
- size = pI830->PciInfo->rom_size;
+ size = intel->PciInfo->rom_size;
if (size == 0) {
size = INTEL_VBIOS_SIZE;
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
@@ -354,7 +354,7 @@ int i830_bios_init(ScrnInfoPtr pScrn)
if (bios == NULL)
return -1;
- ret = pci_device_read_rom(pI830->PciInfo, bios);
+ ret = pci_device_read_rom(intel->PciInfo, bios);
if (ret != 0) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"libpciaccess failed to read %dkB video BIOS: %s\n",
@@ -383,9 +383,9 @@ int i830_bios_init(ScrnInfoPtr pScrn)
bdb_off = vbt_off + vbt->bdb_offset;
bdb = (struct bdb_header *)(bios + bdb_off);
- parse_general_features(pI830, bdb);
- parse_panel_data(pI830, bdb);
- parse_driver_feature(pI830, bdb);
+ parse_general_features(intel, bdb);
+ parse_panel_data(intel, bdb);
+ parse_driver_feature(intel, bdb);
parse_sdvo_mapping(pScrn, bdb);
xfree(bios);
diff --git a/src/i830_dri.c b/src/i830_dri.c
index b9d82b8c..fe738b83 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -84,7 +84,7 @@ I830DRI2CreateBuffers(DrawablePtr pDraw, unsigned int *attachments, int count)
{
ScreenPtr pScreen = pDraw->pScreen;
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
DRI2BufferPtr buffers;
dri_bo *bo;
int i;
@@ -113,7 +113,7 @@ I830DRI2CreateBuffers(DrawablePtr pDraw, unsigned int *attachments, int count)
switch (attachments[i]) {
case DRI2BufferDepth:
- if (SUPPORTS_YTILING(pI830))
+ if (SUPPORTS_YTILING(intel))
hint = INTEL_CREATE_PIXMAP_TILING_Y;
else
hint = INTEL_CREATE_PIXMAP_TILING_X;
@@ -126,7 +126,7 @@ I830DRI2CreateBuffers(DrawablePtr pDraw, unsigned int *attachments, int count)
break;
}
- if (!pI830->tiling)
+ if (!intel->tiling)
hint = 0;
pPixmap = (*pScreen->CreatePixmap) (pScreen,
@@ -165,7 +165,7 @@ I830DRI2CreateBuffer(DrawablePtr pDraw, unsigned int attachment,
{
ScreenPtr pScreen = pDraw->pScreen;
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
DRI2Buffer2Ptr buffer;
dri_bo *bo;
I830DRI2BufferPrivatePtr privates;
@@ -189,7 +189,7 @@ I830DRI2CreateBuffer(DrawablePtr pDraw, unsigned int attachment,
switch (attachment) {
case DRI2BufferDepth:
case DRI2BufferDepthStencil:
- if (SUPPORTS_YTILING(pI830))
+ if (SUPPORTS_YTILING(intel))
hint = INTEL_CREATE_PIXMAP_TILING_Y;
else
hint = INTEL_CREATE_PIXMAP_TILING_X;
@@ -202,7 +202,7 @@ I830DRI2CreateBuffer(DrawablePtr pDraw, unsigned int attachment,
break;
}
- if (!pI830->tiling)
+ if (!intel->tiling)
hint = 0;
pPixmap = (*pScreen->CreatePixmap) (pScreen,
@@ -278,7 +278,7 @@ I830DRI2CopyRegion(DrawablePtr pDraw, RegionPtr pRegion,
I830DRI2BufferPrivatePtr dstPrivate = pDstBuffer->driverPrivate;
ScreenPtr pScreen = pDraw->pScreen;
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
DrawablePtr src = (srcPrivate->attachment == DRI2BufferFrontLeft)
? pDraw : &srcPrivate->pPixmap->drawable;
DrawablePtr dst = (dstPrivate->attachment == DRI2BufferFrontLeft)
@@ -294,7 +294,7 @@ I830DRI2CopyRegion(DrawablePtr pDraw, RegionPtr pRegion,
/* Wait for the scanline to be outside the region to be copied */
if (pixmap_is_scanout(get_drawable_pixmap(dst))
- && pI830->swapbuffers_wait) {
+ && intel->swapbuffers_wait) {
BoxPtr box;
BoxRec crtcbox;
int y1, y2;
@@ -346,7 +346,7 @@ I830DRI2CopyRegion(DrawablePtr pDraw, RegionPtr pRegion,
* later.
*/
I830EmitFlush(pScrn);
- pI830->need_mi_flush = FALSE;
+ intel->need_mi_flush = FALSE;
/* We can't rely on getting into the block handler before the DRI
* client gets to run again so flush now. */
@@ -354,14 +354,14 @@ I830DRI2CopyRegion(DrawablePtr pDraw, RegionPtr pRegion,
#if ALWAYS_SYNC
I830Sync(pScrn);
#endif
- drmCommandNone(pI830->drmSubFD, DRM_I915_GEM_THROTTLE);
+ drmCommandNone(intel->drmSubFD, DRM_I915_GEM_THROTTLE);
}
Bool I830DRI2ScreenInit(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
DRI2InfoRec info;
char *p;
int i;
@@ -384,7 +384,7 @@ Bool I830DRI2ScreenInit(ScreenPtr pScreen)
}
#endif
- info.fd = pI830->drmSubFD;
+ info.fd = intel->drmSubFD;
/* The whole drmOpen thing is a fiasco and we need to find a way
* back to just using open(2). For now, however, lets just make
@@ -394,7 +394,7 @@ Bool I830DRI2ScreenInit(ScreenPtr pScreen)
fstat(info.fd, &sbuf);
d = sbuf.st_rdev;
- p = pI830->deviceName;
+ p = intel->deviceName;
for (i = 0; i < DRM_MAX_MINOR; i++) {
sprintf(p, DRM_DEV_NAME, DRM_DIR_NAME, i);
if (stat(p, &sbuf) == 0 && sbuf.st_rdev == d)
@@ -406,7 +406,7 @@ Bool I830DRI2ScreenInit(ScreenPtr pScreen)
return FALSE;
}
- info.driverName = IS_I965G(pI830) ? "i965" : "i915";
+ info.driverName = IS_I965G(intel) ? "i965" : "i915";
info.deviceName = p;
#if DRI2INFOREC_VERSION >= 3
@@ -435,8 +435,8 @@ Bool I830DRI2ScreenInit(ScreenPtr pScreen)
void I830DRI2CloseScreen(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
DRI2CloseScreen(pScreen);
- pI830->directRenderingType = DRI_NONE;
+ intel->directRenderingType = DRI_NONE;
}
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 56d86fcc..dbf6c11e 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -226,24 +226,24 @@ const OptionInfoRec *I830AvailableOptions(int chipid, int busid)
static Bool I830GetRec(ScrnInfoPtr pScrn)
{
- I830Ptr pI830;
+ intel_screen_private *intel;
if (pScrn->driverPrivate)
return TRUE;
- pI830 = pScrn->driverPrivate = xnfcalloc(sizeof(I830Rec), 1);
+ intel = pScrn->driverPrivate = xnfcalloc(sizeof(intel_screen_private), 1);
return TRUE;
}
static void I830FreeRec(ScrnInfoPtr pScrn)
{
- I830Ptr pI830;
+ intel_screen_private *intel;
if (!pScrn)
return;
if (!pScrn->driverPrivate)
return;
- pI830 = I830PTR(pScrn);
+ intel = intel_get_screen_private(pScrn);
xfree(pScrn->driverPrivate);
pScrn->driverPrivate = NULL;
@@ -332,9 +332,9 @@ I830LoadPalette(ScrnInfoPtr pScrn, int numColors, int *indices,
static Bool i830CreateScreenResources(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
- pScreen->CreateScreenResources = pI830->CreateScreenResources;
+ pScreen->CreateScreenResources = intel->CreateScreenResources;
if (!(*pScreen->CreateScreenResources) (pScreen))
return FALSE;
@@ -351,15 +351,15 @@ static void PreInitCleanup(ScrnInfoPtr pScrn)
/*
* Adjust *width to allow for tiling if possible
*/
-Bool i830_tiled_width(I830Ptr i830, int *width, int cpp)
+Bool i830_tiled_width(intel_screen_private *intel, int *width, int cpp)
{
Bool tiled = FALSE;
/*
* Adjust the display width to allow for front buffer tiling if possible
*/
- if (i830->tiling) {
- if (IS_I965G(i830)) {
+ if (intel->tiling) {
+ if (IS_I965G(intel)) {
int tile_pixels = 512 / cpp;
*width = (*width + tile_pixels - 1) &
~(tile_pixels - 1);
@@ -400,7 +400,7 @@ int i830_pad_drawable_width(int width, int cpp)
static Bool i830_xf86crtc_resize(ScrnInfoPtr scrn, int width, int height)
{
#ifdef DRI2
- I830Ptr i830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
int old_width = scrn->displayWidth;
#endif
int old_x = scrn->virtualX;
@@ -412,13 +412,13 @@ static Bool i830_xf86crtc_resize(ScrnInfoPtr scrn, int width, int height)
scrn->virtualX = width;
scrn->virtualY = height;
#ifdef DRI2
- if (i830->front_buffer) {
+ if (intel->front_buffer) {
i830_memory *new_front, *old_front;
Bool tiled;
ScreenPtr screen = screenInfo.screens[scrn->scrnIndex];
- scrn->displayWidth = i830_pad_drawable_width(width, i830->cpp);
- tiled = i830_tiled_width(i830, &scrn->displayWidth, i830->cpp);
+ scrn->displayWidth = i830_pad_drawable_width(width, intel->cpp);
+ tiled = i830_tiled_width(intel, &scrn->displayWidth, intel->cpp);
xf86DrvMsg(scrn->scrnIndex, X_INFO,
"Allocate new frame buffer %dx%d stride %d\n", width,
height, scrn->displayWidth);
@@ -431,15 +431,15 @@ static Bool i830_xf86crtc_resize(ScrnInfoPtr scrn, int width, int height)
scrn->displayWidth = old_width;
return FALSE;
}
- old_front = i830->front_buffer;
- i830->front_buffer = new_front;
+ old_front = intel->front_buffer;
+ intel->front_buffer = new_front;
i830_set_pixmap_bo(screen->GetScreenPixmap(screen),
new_front->bo);
- scrn->fbOffset = i830->front_buffer->offset;
+ scrn->fbOffset = intel->front_buffer->offset;
screen->ModifyPixmapHeader(screen->GetScreenPixmap(screen),
width, height, -1, -1,
- scrn->displayWidth * i830->cpp,
+ scrn->displayWidth * intel->cpp,
NULL);
/* ick. xf86EnableDisableFBAccess smashes the screen pixmap devPrivate,
@@ -448,7 +448,7 @@ static Bool i830_xf86crtc_resize(ScrnInfoPtr scrn, int width, int height)
scrn->pixmapPrivate.ptr = NULL;
xf86DrvMsg(scrn->scrnIndex, X_INFO,
"New front buffer at 0x%lx\n",
- i830->front_buffer->offset);
+ intel->front_buffer->offset);
i830_set_new_crtc_bo(scrn);
I830Sync(scrn);
i830WaitForVblank(scrn);
@@ -498,12 +498,12 @@ static Bool i830_kernel_mode_enabled(ScrnInfoPtr pScrn)
static void i830_detect_chipset(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
MessageType from = X_PROBED;
const char *chipname;
uint32_t capid;
- switch (DEVICE_ID(pI830->PciInfo)) {
+ switch (DEVICE_ID(intel->PciInfo)) {
case PCI_CHIP_I830_M:
chipname = "830M";
break;
@@ -512,10 +512,10 @@ static void i830_detect_chipset(ScrnInfoPtr pScrn)
break;
case PCI_CHIP_I855_GM:
/* Check capid register to find the chipset variant */
- pci_device_cfg_read_u32(pI830->PciInfo, &capid, I85X_CAPID);
- pI830->variant =
+ pci_device_cfg_read_u32(intel->PciInfo, &capid, I85X_CAPID);
+ intel->variant =
(capid >> I85X_VARIANT_SHIFT) & I85X_VARIANT_MASK;
- switch (pI830->variant) {
+ switch (intel->variant) {
case I855_GM:
chipname = "855GM";
break;
@@ -531,7 +531,7 @@ static void i830_detect_chipset(ScrnInfoPtr pScrn)
default:
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Unknown 852GM/855GM variant: 0x%x)\n",
- pI830->variant);
+ intel->variant);
chipname = "852GM/855GM (unknown variant)";
break;
}
@@ -622,28 +622,28 @@ static void i830_detect_chipset(ScrnInfoPtr pScrn)
"Integrated Graphics Chipset: Intel(R) %s\n", chipname);
/* Set the Chipset and ChipRev, allowing config file entries to override. */
- if (pI830->pEnt->device->chipset && *pI830->pEnt->device->chipset) {
- pScrn->chipset = pI830->pEnt->device->chipset;
+ if (intel->pEnt->device->chipset && *intel->pEnt->device->chipset) {
+ pScrn->chipset = intel->pEnt->device->chipset;
from = X_CONFIG;
- } else if (pI830->pEnt->device->chipID >= 0) {
+ } else if (intel->pEnt->device->chipID >= 0) {
pScrn->chipset = (char *)xf86TokenToString(I830Chipsets,
- pI830->pEnt->device->
+ intel->pEnt->device->
chipID);
from = X_CONFIG;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"ChipID override: 0x%04X\n",
- pI830->pEnt->device->chipID);
- DEVICE_ID(pI830->PciInfo) = pI830->pEnt->device->chipID;
+ intel->pEnt->device->chipID);
+ DEVICE_ID(intel->PciInfo) = intel->pEnt->device->chipID;
} else {
from = X_PROBED;
pScrn->chipset = (char *)xf86TokenToString(I830Chipsets,
- DEVICE_ID(pI830->
+ DEVICE_ID(intel->
PciInfo));
}
- if (pI830->pEnt->device->chipRev >= 0) {
+ if (intel->pEnt->device->chipRev >= 0) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ChipRev override: %d\n",
- pI830->pEnt->device->chipRev);
+ intel->pEnt->device->chipRev);
}
xf86DrvMsg(pScrn->scrnIndex, from, "Chipset: \"%s\"\n",
@@ -652,16 +652,16 @@ static void i830_detect_chipset(ScrnInfoPtr pScrn)
static Bool I830GetEarlyOptions(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
/* Process the options */
xf86CollectOptions(pScrn, NULL);
- if (!(pI830->Options = xalloc(sizeof(I830Options))))
+ if (!(intel->Options = xalloc(sizeof(I830Options))))
return FALSE;
- memcpy(pI830->Options, I830Options, sizeof(I830Options));
- xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, pI830->Options);
+ memcpy(intel->Options, I830Options, sizeof(I830Options));
+ xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, intel->Options);
- pI830->fallback_debug = xf86ReturnOptValBool(pI830->Options,
+ intel->fallback_debug = xf86ReturnOptValBool(intel->Options,
OPTION_FALLBACKDEBUG,
FALSE);
@@ -670,23 +670,23 @@ static Bool I830GetEarlyOptions(ScrnInfoPtr pScrn)
static void i830_check_dri_option(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
- pI830->directRenderingType = DRI_NONE;
- if (!xf86ReturnOptValBool(pI830->Options, OPTION_DRI, TRUE))
- pI830->directRenderingType = DRI_DISABLED;
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
+ intel->directRenderingType = DRI_NONE;
+ if (!xf86ReturnOptValBool(intel->Options, OPTION_DRI, TRUE))
+ intel->directRenderingType = DRI_DISABLED;
if (pScrn->depth != 16 && pScrn->depth != 24) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"DRI is disabled because it "
"runs only at depths 16 and 24.\n");
- pI830->directRenderingType = DRI_DISABLED;
+ intel->directRenderingType = DRI_DISABLED;
}
}
static Bool i830_open_drm_master(ScrnInfoPtr scrn)
{
- I830Ptr i830 = I830PTR(scrn);
- struct pci_device *dev = i830->PciInfo;
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+ struct pci_device *dev = intel->PciInfo;
char *busid;
drmSetVersion sv;
struct drm_i915_getparam gp;
@@ -696,8 +696,8 @@ static Bool i830_open_drm_master(ScrnInfoPtr scrn)
busid = XNFprintf("pci:%04x:%02x:%02x.%d",
dev->domain, dev->bus, dev->dev, dev->func);
- i830->drmSubFD = drmOpen("i915", busid);
- if (i830->drmSubFD == -1) {
+ intel->drmSubFD = drmOpen("i915", busid);
+ if (intel->drmSubFD == -1) {
xfree(busid);
xf86DrvMsg(scrn->scrnIndex, X_ERROR,
"[drm] Failed to open DRM device for %s: %s\n",
@@ -715,25 +715,25 @@ static Bool i830_open_drm_master(ScrnInfoPtr scrn)
sv.drm_di_minor = 1;
sv.drm_dd_major = -1;
sv.drm_dd_minor = -1;
- err = drmSetInterfaceVersion(i830->drmSubFD, &sv);
+ err = drmSetInterfaceVersion(intel->drmSubFD, &sv);
if (err != 0) {
xf86DrvMsg(scrn->scrnIndex, X_ERROR,
"[drm] failed to set drm interface version.\n");
- drmClose(i830->drmSubFD);
- i830->drmSubFD = -1;
+ drmClose(intel->drmSubFD);
+ intel->drmSubFD = -1;
return FALSE;
}
has_gem = FALSE;
gp.param = I915_PARAM_HAS_GEM;
gp.value = &has_gem;
- (void)drmCommandWriteRead(i830->drmSubFD, DRM_I915_GETPARAM,
+ (void)drmCommandWriteRead(intel->drmSubFD, DRM_I915_GETPARAM,
&gp, sizeof(gp));
if (!has_gem) {
xf86DrvMsg(scrn->scrnIndex, X_ERROR,
"[drm] Failed to detect GEM. Kernel 2.6.28 required.\n");
- drmClose(i830->drmSubFD);
- i830->drmSubFD = -1;
+ drmClose(intel->drmSubFD);
+ intel->drmSubFD = -1;
return FALSE;
}
@@ -742,18 +742,18 @@ static Bool i830_open_drm_master(ScrnInfoPtr scrn)
static void i830_close_drm_master(ScrnInfoPtr scrn)
{
- I830Ptr i830 = I830PTR(scrn);
- if (i830 && i830->drmSubFD > 0) {
- drmClose(i830->drmSubFD);
- i830->drmSubFD = -1;
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+ if (intel && intel->drmSubFD > 0) {
+ drmClose(intel->drmSubFD);
+ intel->drmSubFD = -1;
}
}
static Bool I830DrmModeInit(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
- if (drmmode_pre_init(pScrn, pI830->drmSubFD, pI830->cpp) == FALSE) {
+ if (drmmode_pre_init(pScrn, intel->drmSubFD, intel->cpp) == FALSE) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Kernel modesetting setup failed\n");
PreInitCleanup(pScrn);
@@ -767,27 +767,27 @@ static Bool I830DrmModeInit(ScrnInfoPtr pScrn)
static void I830XvInit(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
MessageType from = X_PROBED;
- pI830->XvPreferOverlay =
- xf86ReturnOptValBool(pI830->Options, OPTION_PREFER_OVERLAY, FALSE);
+ intel->XvPreferOverlay =
+ xf86ReturnOptValBool(intel->Options, OPTION_PREFER_OVERLAY, FALSE);
- if (xf86GetOptValInteger(pI830->Options, OPTION_VIDEO_KEY,
- &(pI830->colorKey))) {
+ if (xf86GetOptValInteger(intel->Options, OPTION_VIDEO_KEY,
+ &(intel->colorKey))) {
from = X_CONFIG;
- } else if (xf86GetOptValInteger(pI830->Options, OPTION_COLOR_KEY,
- &(pI830->colorKey))) {
+ } else if (xf86GetOptValInteger(intel->Options, OPTION_COLOR_KEY,
+ &(intel->colorKey))) {
from = X_CONFIG;
} else {
- pI830->colorKey =
+ intel->colorKey =
(1 << pScrn->offset.red) | (1 << pScrn->offset.green) |
(((pScrn->mask.blue >> pScrn->offset.blue) - 1) <<
pScrn->offset.blue);
from = X_DEFAULT;
}
xf86DrvMsg(pScrn->scrnIndex, from, "video overlay key set to 0x%x\n",
- pI830->colorKey);
+ intel->colorKey);
}
/**
@@ -805,7 +805,7 @@ static void I830XvInit(ScrnInfoPtr pScrn)
*/
static Bool I830PreInit(ScrnInfoPtr pScrn, int flags)
{
- I830Ptr pI830;
+ intel_screen_private *intel;
rgb defaultWeight = { 0, 0, 0 };
EntityInfoPtr pEnt;
int flags24;
@@ -831,15 +831,15 @@ static Bool I830PreInit(ScrnInfoPtr pScrn, int flags)
if (!I830GetRec(pScrn))
return FALSE;
- pI830 = I830PTR(pScrn);
- pI830->pEnt = pEnt;
+ intel = intel_get_screen_private(pScrn);
+ intel->pEnt = pEnt;
pScrn->displayWidth = 640; /* default it */
- if (pI830->pEnt->location.type != BUS_PCI)
+ if (intel->pEnt->location.type != BUS_PCI)
return FALSE;
- pI830->PciInfo = xf86GetPciInfoForEntity(pI830->pEnt->index);
+ intel->PciInfo = xf86GetPciInfoForEntity(intel->pEnt->index);
if (!i830_open_drm_master(pScrn))
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -873,7 +873,7 @@ static Bool I830PreInit(ScrnInfoPtr pScrn, int flags)
if (!xf86SetDefaultVisual(pScrn, -1))
return FALSE;
- pI830->cpp = pScrn->bitsPerPixel / 8;
+ intel->cpp = pScrn->bitsPerPixel / 8;
if (!I830GetEarlyOptions(pScrn))
return FALSE;
@@ -909,8 +909,8 @@ static Bool I830PreInit(ScrnInfoPtr pScrn, int flags)
}
/* Load the dri2 module if requested. */
- if (xf86ReturnOptValBool(pI830->Options, OPTION_DRI, FALSE) &&
- pI830->directRenderingType != DRI_DISABLED) {
+ if (xf86ReturnOptValBool(intel->Options, OPTION_DRI, FALSE) &&
+ intel->directRenderingType != DRI_DISABLED) {
xf86LoadSubModule(pScrn, "dri2");
}
@@ -931,16 +931,16 @@ enum pipe {
*/
void IntelEmitInvarientState(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
/* If we've emitted our state since the last clobber by another client,
* skip it.
*/
- if (pI830->last_3d != LAST_3D_OTHER)
+ if (intel->last_3d != LAST_3D_OTHER)
return;
- if (!IS_I965G(pI830)) {
- if (IS_I9XX(pI830))
+ if (!IS_I965G(intel)) {
+ if (IS_I9XX(intel))
I915EmitInvarientState(pScrn);
else
I830EmitInvarientState(pScrn);
@@ -952,13 +952,13 @@ I830BlockHandler(int i, pointer blockData, pointer pTimeout, pointer pReadmask)
{
ScreenPtr pScreen = screenInfo.screens[i];
ScrnInfoPtr pScrn = xf86Screens[i];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
- pScreen->BlockHandler = pI830->BlockHandler;
+ pScreen->BlockHandler = intel->BlockHandler;
(*pScreen->BlockHandler) (i, blockData, pTimeout, pReadmask);
- pI830->BlockHandler = pScreen->BlockHandler;
+ intel->BlockHandler = pScreen->BlockHandler;
pScreen->BlockHandler = I830BlockHandler;
if (pScrn->vtSema) {
@@ -967,7 +967,7 @@ I830BlockHandler(int i, pointer blockData, pointer pTimeout, pointer pReadmask)
* rendering results may not hit the framebuffer until significantly
* later.
*/
- if (pI830->need_mi_flush || pI830->batch_used) {
+ if (intel->need_mi_flush || intel->batch_used) {
flushed = TRUE;
I830EmitFlush(pScrn);
}
@@ -976,9 +976,9 @@ I830BlockHandler(int i, pointer blockData, pointer pTimeout, pointer pReadmask)
* fashion.
*/
intel_batch_flush(pScrn, flushed);
- drmCommandNone(pI830->drmSubFD, DRM_I915_GEM_THROTTLE);
+ drmCommandNone(intel->drmSubFD, DRM_I915_GEM_THROTTLE);
- pI830->need_mi_flush = FALSE;
+ intel->need_mi_flush = FALSE;
}
i830_uxa_block_handler(pScreen);
@@ -989,7 +989,7 @@ I830BlockHandler(int i, pointer blockData, pointer pTimeout, pointer pReadmask)
static void i830_fixup_mtrrs(ScrnInfoPtr pScrn)
{
#ifdef HAS_MTRR_SUPPORT
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
int fd;
struct mtrr_gentry gentry;
struct mtrr_sentry sentry;
@@ -1008,8 +1008,8 @@ static void i830_fixup_mtrrs(ScrnInfoPtr pScrn)
* The Xserver common layer will then setup the right range
* for us.
*/
- if (gentry.base == pI830->LinearAddr &&
- gentry.size < pI830->FbMapSize) {
+ if (gentry.base == intel->LinearAddr &&
+ gentry.size < intel->FbMapSize) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Removing bad MTRR range (base 0x%lx, size 0x%x)\n",
@@ -1032,8 +1032,8 @@ static void i830_fixup_mtrrs(ScrnInfoPtr pScrn)
static Bool i830_try_memory_allocation(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
- Bool tiled = pI830->tiling;
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
+ Bool tiled = intel->tiling;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Attempting memory allocation with %stiled buffers.\n",
@@ -1063,11 +1063,11 @@ failed:
*/
static Bool i830_memory_init(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
int savedDisplayWidth = pScrn->displayWidth;
Bool tiled = FALSE;
- tiled = i830_tiled_width(pI830, &pScrn->displayWidth, pI830->cpp);
+ tiled = i830_tiled_width(intel, &pScrn->displayWidth, intel->cpp);
/* Set up our video memory allocator for the chosen videoRam */
if (!i830_allocator_init(pScrn, pScrn->videoRam * KB(1))) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -1077,7 +1077,7 @@ static Bool i830_memory_init(ScrnInfoPtr pScrn)
}
xf86DrvMsg(pScrn->scrnIndex,
- pI830->pEnt->device->videoRam ? X_CONFIG : X_DEFAULT,
+ intel->pEnt->device->videoRam ? X_CONFIG : X_DEFAULT,
"VideoRam: %d KB\n", pScrn->videoRam);
/* Tiled first if we got a good displayWidth */
@@ -1086,7 +1086,7 @@ static Bool i830_memory_init(ScrnInfoPtr pScrn)
return TRUE;
else {
i830_reset_allocations(pScrn);
- pI830->tiling = FALSE;
+ intel->tiling = FALSE;
}
}
@@ -1101,20 +1101,20 @@ static Bool i830_memory_init(ScrnInfoPtr pScrn)
void i830_init_bufmgr(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
int batch_size;
- if (pI830->bufmgr)
+ if (intel->bufmgr)
return;
batch_size = 4096 * 4;
/* The 865 has issues with larger-than-page-sized batch buffers. */
- if (IS_I865G(pI830))
+ if (IS_I865G(intel))
batch_size = 4096;
- pI830->bufmgr = intel_bufmgr_gem_init(pI830->drmSubFD, batch_size);
- intel_bufmgr_gem_enable_reuse(pI830->bufmgr);
+ intel->bufmgr = intel_bufmgr_gem_init(intel->drmSubFD, batch_size);
+ intel_bufmgr_gem_enable_reuse(intel->bufmgr);
}
Bool i830_crtc_on(xf86CrtcPtr crtc)
@@ -1139,23 +1139,23 @@ Bool i830_crtc_on(xf86CrtcPtr crtc)
int i830_crtc_to_pipe(xf86CrtcPtr crtc)
{
ScrnInfoPtr pScrn = crtc->scrn;
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
- return drmmode_get_pipe_from_crtc_id(pI830->bufmgr, crtc);
+ return drmmode_get_pipe_from_crtc_id(intel->bufmgr, crtc);
}
static Bool
I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];;
- I830Ptr pI830 = I830PTR(pScrn);;
+ intel_screen_private *intel = intel_get_screen_private(pScrn);;
VisualPtr visual;
MessageType from;
- struct pci_device *const device = pI830->PciInfo;
- int fb_bar = IS_I9XX(pI830) ? 2 : 0;
+ struct pci_device *const device = intel->PciInfo;
+ int fb_bar = IS_I9XX(intel) ? 2 : 0;
pScrn->displayWidth =
- i830_pad_drawable_width(pScrn->virtualX, pI830->cpp);
+ i830_pad_drawable_width(pScrn->virtualX, intel->cpp);
/*
* The "VideoRam" config file parameter specifies the maximum amount of
@@ -1169,13 +1169,13 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
* actual memory allocation, so alignment and things will cause less than
* VideoRam to be actually used.
*/
- if (pI830->pEnt->device->videoRam == 0) {
+ if (intel->pEnt->device->videoRam == 0) {
from = X_DEFAULT;
- pScrn->videoRam = pI830->FbMapSize / KB(1);
+ pScrn->videoRam = intel->FbMapSize / KB(1);
} else {
#if 0
from = X_CONFIG;
- pScrn->videoRam = pI830->pEnt->device->videoRam;
+ pScrn->videoRam = intel->pEnt->device->videoRam;
#else
/* Disable VideoRam configuration, at least for now. Previously,
* VideoRam was necessary to avoid overly low limits on allocated
@@ -1185,9 +1185,9 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
* obsolete.
*/
from = X_DEFAULT;
- pScrn->videoRam = pI830->FbMapSize / KB(1);
+ pScrn->videoRam = intel->FbMapSize / KB(1);
- if (pScrn->videoRam != pI830->pEnt->device->videoRam) {
+ if (pScrn->videoRam != intel->pEnt->device->videoRam) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"VideoRam configuration found, which is no longer "
"recommended.\n");
@@ -1195,7 +1195,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
"Continuing with default %dkB VideoRam instead of %d "
"kB.\n",
pScrn->videoRam,
- pI830->pEnt->device->videoRam);
+ intel->pEnt->device->videoRam);
}
#endif
}
@@ -1203,47 +1203,47 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
pScrn->videoRam = device->regions[fb_bar].size / 1024;
#ifdef DRI2
- if (pI830->directRenderingType == DRI_NONE
+ if (intel->directRenderingType == DRI_NONE
&& I830DRI2ScreenInit(pScreen))
- pI830->directRenderingType = DRI_DRI2;
+ intel->directRenderingType = DRI_DRI2;
#endif
/* Enable tiling by default */
- pI830->tiling = TRUE;
+ intel->tiling = TRUE;
/* Allow user override if they set a value */
- if (xf86IsOptionSet(pI830->Options, OPTION_TILING)) {
- if (xf86ReturnOptValBool(pI830->Options, OPTION_TILING, FALSE))
- pI830->tiling = TRUE;
+ if (xf86IsOptionSet(intel->Options, OPTION_TILING)) {
+ if (xf86ReturnOptValBool(intel->Options, OPTION_TILING, FALSE))
+ intel->tiling = TRUE;
else
- pI830->tiling = FALSE;
+ intel->tiling = FALSE;
}
/* SwapBuffers delays to avoid tearing */
- pI830->swapbuffers_wait = TRUE;
+ intel->swapbuffers_wait = TRUE;
/* Allow user override if they set a value */
- if (xf86IsOptionSet(pI830->Options, OPTION_SWAPBUFFERS_WAIT)) {
+ if (xf86IsOptionSet(intel->Options, OPTION_SWAPBUFFERS_WAIT)) {
if (xf86ReturnOptValBool
- (pI830->Options, OPTION_SWAPBUFFERS_WAIT, FALSE))
- pI830->swapbuffers_wait = TRUE;
+ (intel->Options, OPTION_SWAPBUFFERS_WAIT, FALSE))
+ intel->swapbuffers_wait = TRUE;
else
- pI830->swapbuffers_wait = FALSE;
+ intel->swapbuffers_wait = FALSE;
}
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Tiling %sabled\n",
- pI830->tiling ? "en" : "dis");
+ intel->tiling ? "en" : "dis");
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "SwapBuffers wait %sabled\n",
- pI830->swapbuffers_wait ? "en" : "dis");
+ intel->swapbuffers_wait ? "en" : "dis");
- pI830->last_3d = LAST_3D_OTHER;
- pI830->overlayOn = FALSE;
+ intel->last_3d = LAST_3D_OTHER;
+ intel->overlayOn = FALSE;
/*
* Set this so that the overlay allocation is factored in when
* appropriate.
*/
- pI830->XvEnabled = TRUE;
+ intel->XvEnabled = TRUE;
if (!i830_memory_init(pScrn)) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -1270,7 +1270,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
* set the initial framebuffer pixmap to point at
* it
*/
- pScrn->fbOffset = pI830->front_buffer->offset;
+ pScrn->fbOffset = intel->front_buffer->offset;
DPRINTF(PFX, "assert( if(!fbScreenInit(pScreen, ...) )\n");
if (!fbScreenInit(pScreen, NULL,
@@ -1304,12 +1304,12 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
return FALSE;
}
- if (IS_I965G(pI830))
- pI830->batch_flush_notify = i965_batch_flush_notify;
- else if (IS_I9XX(pI830))
- pI830->batch_flush_notify = i915_batch_flush_notify;
+ if (IS_I965G(intel))
+ intel->batch_flush_notify = i965_batch_flush_notify;
+ else if (IS_I9XX(intel))
+ intel->batch_flush_notify = i915_batch_flush_notify;
else
- pI830->batch_flush_notify = i830_batch_flush_notify;
+ intel->batch_flush_notify = i830_batch_flush_notify;
miInitializeBackingStore(pScreen);
xf86SetBackingStore(pScreen);
@@ -1338,13 +1338,13 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
if (!I830EnterVT(scrnIndex, 0))
return FALSE;
- pI830->BlockHandler = pScreen->BlockHandler;
+ intel->BlockHandler = pScreen->BlockHandler;
pScreen->BlockHandler = I830BlockHandler;
pScreen->SaveScreen = xf86SaveScreen;
- pI830->CloseScreen = pScreen->CloseScreen;
+ intel->CloseScreen = pScreen->CloseScreen;
pScreen->CloseScreen = I830CloseScreen;
- pI830->CreateScreenResources = pScreen->CreateScreenResources;
+ intel->CreateScreenResources = pScreen->CreateScreenResources;
pScreen->CreateScreenResources = i830CreateScreenResources;
if (!xf86CrtcScreenInit(pScreen))
@@ -1364,24 +1364,24 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
xf86DPMSInit(pScreen, xf86DPMSSet, 0);
#ifdef INTEL_XVMC
- pI830->XvMCEnabled = FALSE;
- from = ((pI830->directRenderingType == DRI_DRI2) &&
- xf86GetOptValBool(pI830->Options, OPTION_XVMC,
- &pI830->XvMCEnabled) ? X_CONFIG : X_DEFAULT);
+ intel->XvMCEnabled = FALSE;
+ from = ((intel->directRenderingType == DRI_DRI2) &&
+ xf86GetOptValBool(intel->Options, OPTION_XVMC,
+ &intel->XvMCEnabled) ? X_CONFIG : X_DEFAULT);
xf86DrvMsg(pScrn->scrnIndex, from, "Intel XvMC decoder %sabled\n",
- pI830->XvMCEnabled ? "en" : "dis");
+ intel->XvMCEnabled ? "en" : "dis");
#endif
/* Init video */
- if (pI830->XvEnabled)
+ if (intel->XvEnabled)
I830InitVideo(pScreen);
/* Setup 3D engine, needed for rotation too */
IntelEmitInvarientState(pScrn);
#if defined(DRI2)
- switch (pI830->directRenderingType) {
+ switch (intel->directRenderingType) {
case DRI_DRI2:
- pI830->directRenderingOpen = TRUE;
+ intel->directRenderingOpen = TRUE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"direct rendering: DRI2 Enabled\n");
break;
@@ -1402,7 +1402,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
if (serverGeneration == 1)
xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options);
- pI830->suspended = FALSE;
+ intel->suspended = FALSE;
return TRUE;
}
@@ -1415,8 +1415,8 @@ static void I830FreeScreen(int scrnIndex, int flags)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
#ifdef INTEL_XVMC
- I830Ptr pI830 = I830PTR(pScrn);
- if (pI830 && pI830->XvMCEnabled)
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
+ if (intel && intel->XvMCEnabled)
intel_xvmc_finish(xf86Screens[scrnIndex]);
#endif
@@ -1430,7 +1430,7 @@ static void I830FreeScreen(int scrnIndex, int flags)
static void I830LeaveVT(int scrnIndex, int flags)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
int ret;
DPRINTF(PFX, "Leave VT\n");
@@ -1443,10 +1443,10 @@ static void I830LeaveVT(int scrnIndex, int flags)
intel_batch_teardown(pScrn);
- if (IS_I965G(pI830))
+ if (IS_I965G(intel))
gen4_render_state_cleanup(pScrn);
- ret = drmDropMaster(pI830->drmSubFD);
+ ret = drmDropMaster(intel->drmSubFD);
if (ret)
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"drmDropMaster failed: %s\n", strerror(errno));
@@ -1458,12 +1458,12 @@ static void I830LeaveVT(int scrnIndex, int flags)
static Bool I830EnterVT(int scrnIndex, int flags)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
int ret;
DPRINTF(PFX, "Enter VT\n");
- ret = drmSetMaster(pI830->drmSubFD);
+ ret = drmSetMaster(intel->drmSubFD);
if (ret) {
if (errno == EINVAL) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
@@ -1483,14 +1483,14 @@ static Bool I830EnterVT(int scrnIndex, int flags)
intel_batch_init(pScrn);
- if (IS_I965G(pI830))
+ if (IS_I965G(intel))
gen4_render_state_init(pScrn);
if (!xf86SetDesiredModes(pScrn))
return FALSE;
/* Mark 3D state as being clobbered and setup the basics */
- pI830->last_3d = LAST_3D_OTHER;
+ intel->last_3d = LAST_3D_OTHER;
IntelEmitInvarientState(pScrn);
return TRUE;
@@ -1506,21 +1506,21 @@ static Bool I830SwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
static Bool I830CloseScreen(int scrnIndex, ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
if (pScrn->vtSema == TRUE) {
I830LeaveVT(scrnIndex, 0);
}
- if (pI830->uxa_driver) {
+ if (intel->uxa_driver) {
uxa_driver_fini(pScreen);
- xfree(pI830->uxa_driver);
- pI830->uxa_driver = NULL;
+ xfree(intel->uxa_driver);
+ intel->uxa_driver = NULL;
}
- if (pI830->front_buffer) {
+ if (intel->front_buffer) {
i830_set_pixmap_bo(pScreen->GetScreenPixmap(pScreen), NULL);
- i830_free_memory(pScrn, pI830->front_buffer);
- pI830->front_buffer = NULL;
+ i830_free_memory(pScrn, intel->front_buffer);
+ intel->front_buffer = NULL;
}
xf86_cursors_fini(pScreen);
@@ -1529,12 +1529,12 @@ static Bool I830CloseScreen(int scrnIndex, ScreenPtr pScreen)
i965_free_video(pScrn);
- pScreen->CloseScreen = pI830->CloseScreen;
+ pScreen->CloseScreen = intel->CloseScreen;
(*pScreen->CloseScreen) (scrnIndex, pScreen);
- if (pI830->directRenderingOpen
- && pI830->directRenderingType == DRI_DRI2) {
- pI830->directRenderingOpen = FALSE;
+ if (intel->directRenderingOpen
+ && intel->directRenderingType == DRI_DRI2) {
+ intel->directRenderingOpen = FALSE;
I830DRI2CloseScreen(pScreen);
}
@@ -1573,7 +1573,7 @@ I830ValidMode(int scrnIndex, DisplayModePtr mode, Bool verbose, int flags)
static Bool I830PMEvent(int scrnIndex, pmEvent event, Bool undo)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
DPRINTF(PFX, "Enter VT, event %d, undo: %s\n", event,
BOOLTOSTRING(undo));
@@ -1584,23 +1584,23 @@ static Bool I830PMEvent(int scrnIndex, pmEvent event, Bool undo)
case XF86_APM_USER_SUSPEND:
case XF86_APM_SYS_STANDBY:
case XF86_APM_USER_STANDBY:
- if (!undo && !pI830->suspended) {
+ if (!undo && !intel->suspended) {
pScrn->LeaveVT(scrnIndex, 0);
- pI830->suspended = TRUE;
+ intel->suspended = TRUE;
sleep(SUSPEND_SLEEP);
- } else if (undo && pI830->suspended) {
+ } else if (undo && intel->suspended) {
sleep(RESUME_SLEEP);
pScrn->EnterVT(scrnIndex, 0);
- pI830->suspended = FALSE;
+ intel->suspended = FALSE;
}
break;
case XF86_APM_STANDBY_RESUME:
case XF86_APM_NORMAL_RESUME:
case XF86_APM_CRITICAL_RESUME:
- if (pI830->suspended) {
+ if (intel->suspended) {
sleep(RESUME_SLEEP);
pScrn->EnterVT(scrnIndex, 0);
- pI830->suspended = FALSE;
+ intel->suspended = FALSE;
/*
* Turn the screen saver off when resuming. This seems to be
* needed to stop xscreensaver kicking in (when used).
diff --git a/src/i830_hwmc.c b/src/i830_hwmc.c
index 896cd94b..1233e0a7 100644
--- a/src/i830_hwmc.c
+++ b/src/i830_hwmc.c
@@ -49,20 +49,20 @@ static Bool intel_xvmc_set_driver(struct intel_xvmc_driver *d)
/* This must be first called! */
Bool intel_xvmc_probe(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
Bool ret = FALSE;
- if (!pI830->XvMCEnabled)
+ if (!intel->XvMCEnabled)
return FALSE;
/* Needs KMS support. */
- if (IS_I915G(pI830) || IS_I915GM(pI830))
+ if (IS_I915G(intel) || IS_I915GM(intel))
return FALSE;
- if (IS_I9XX(pI830)) {
- if (IS_I915(pI830))
+ if (IS_I9XX(intel)) {
+ if (IS_I915(intel))
ret = intel_xvmc_set_driver(&i915_xvmc_driver);
- else if (IS_G4X(pI830) || IS_IGDNG(pI830))
+ else if (IS_G4X(intel) || IS_IGDNG(intel))
ret = intel_xvmc_set_driver(&vld_xvmc_driver);
else
ret = intel_xvmc_set_driver(&i965_xvmc_driver);
@@ -83,7 +83,7 @@ void intel_xvmc_finish(ScrnInfoPtr pScrn)
Bool intel_xvmc_driver_init(ScreenPtr pScreen, XF86VideoAdaptorPtr xv_adaptor)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
struct drm_i915_setparam sp;
int ret;
@@ -100,7 +100,7 @@ Bool intel_xvmc_driver_init(ScreenPtr pScreen, XF86VideoAdaptorPtr xv_adaptor)
/* Currently XvMC uses batchbuffer */
sp.param = I915_SETPARAM_ALLOW_BATCHBUFFER;
sp.value = 1;
- ret = drmCommandWrite(pI830->drmSubFD, DRM_I915_SETPARAM,
+ ret = drmCommandWrite(intel->drmSubFD, DRM_I915_SETPARAM,
&sp, sizeof(sp));
if (ret == 0)
return TRUE;
@@ -111,7 +111,7 @@ Bool intel_xvmc_driver_init(ScreenPtr pScreen, XF86VideoAdaptorPtr xv_adaptor)
Bool intel_xvmc_screen_init(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
char buf[64];
if (!xvmc_driver)
@@ -123,15 +123,15 @@ Bool intel_xvmc_screen_init(ScreenPtr pScreen)
xvmc_driver->name);
} else {
intel_xvmc_finish(pScrn);
- pI830->XvMCEnabled = FALSE;
+ intel->XvMCEnabled = FALSE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"[XvMC] Failed to initialize XvMC.\n");
return FALSE;
}
sprintf(buf, "pci:%04x:%02x:%02x.%d",
- pI830->PciInfo->domain,
- pI830->PciInfo->bus, pI830->PciInfo->dev, pI830->PciInfo->func);
+ intel->PciInfo->domain,
+ intel->PciInfo->bus, intel->PciInfo->dev, intel->PciInfo->func);
xf86XvMCRegisterDRInfo(pScreen, INTEL_XVMC_LIBNAME,
buf,
@@ -142,7 +142,7 @@ Bool intel_xvmc_screen_init(ScreenPtr pScreen)
Bool intel_xvmc_init_batch(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
int size = KB(64);
if (!i830_allocate_xvmc_buffer(pScrn, "[XvMC] batch buffer",
@@ -150,9 +150,9 @@ Bool intel_xvmc_init_batch(ScrnInfoPtr pScrn)
ALIGN_BOTH_ENDS))
return FALSE;
- if (drmAddMap(pI830->drmSubFD,
+ if (drmAddMap(intel->drmSubFD,
(drm_handle_t) (xvmc_driver->batch->offset +
- pI830->LinearAddr),
+ intel->LinearAddr),
xvmc_driver->batch->size, DRM_AGP, 0,
&xvmc_driver->batch_handle) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -164,10 +164,10 @@ Bool intel_xvmc_init_batch(ScrnInfoPtr pScrn)
void intel_xvmc_fini_batch(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
if (xvmc_driver->batch_handle) {
- drmRmMap(pI830->drmSubFD, xvmc_driver->batch_handle);
+ drmRmMap(intel->drmSubFD, xvmc_driver->batch_handle);
xvmc_driver->batch_handle = 0;
}
if (xvmc_driver->batch) {
diff --git a/src/i830_memory.c b/src/i830_memory.c
index 83fee898..1730a7c8 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -58,7 +58,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
* only)
*
* The user may request a specific amount of memory to be used
- * (pI830->pEnt->videoRam != 0), in which case allocations have to fit within
+ * (intel->pEnt->videoRam != 0), in which case allocations have to fit within
* that much aperture. If not, the individual allocations will be
* automatically sized, and will be fit within the maximum aperture size.
* Only the actual memory used (not alignment padding) will get actual AGP
@@ -94,19 +94,19 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/**
* Returns the fence size for a tiled area of the given size.
*/
-unsigned long i830_get_fence_size(I830Ptr pI830, unsigned long size)
+unsigned long i830_get_fence_size(intel_screen_private *intel, unsigned long size)
{
unsigned long i;
unsigned long start;
- if (IS_I965G(pI830)) {
+ if (IS_I965G(intel)) {
/* The 965 can have fences at any page boundary. */
return ALIGN(size, GTT_PAGE_SIZE);
} else {
/* Align the size to a power of two greater than the smallest fence
* size.
*/
- if (IS_I9XX(pI830))
+ if (IS_I9XX(intel))
start = MB(1);
else
start = KB(512);
@@ -122,7 +122,7 @@ unsigned long i830_get_fence_size(I830Ptr pI830, unsigned long size)
* calculate that here.
*/
unsigned long
-i830_get_fence_pitch(I830Ptr pI830, unsigned long pitch, int format)
+i830_get_fence_pitch(intel_screen_private *intel, unsigned long pitch, int format)
{
unsigned long i;
unsigned long tile_width = (format == I915_TILING_Y) ? 128 : 512;
@@ -131,7 +131,7 @@ i830_get_fence_pitch(I830Ptr pI830, unsigned long pitch, int format)
return pitch;
/* 965 is flexible */
- if (IS_I965G(pI830))
+ if (IS_I965G(intel))
return ROUND_TO(pitch, tile_width);
/* Pre-965 needs power of two tile width */
@@ -144,29 +144,29 @@ i830_get_fence_pitch(I830Ptr pI830, unsigned long pitch, int format)
* On some chips, pitch width has to be a power of two tile width, so
* calculate that here.
*/
-static unsigned long i830_get_fence_alignment(I830Ptr pI830, unsigned long size)
+static unsigned long i830_get_fence_alignment(intel_screen_private *intel, unsigned long size)
{
- if (IS_I965G(pI830))
+ if (IS_I965G(intel))
return 4096;
else
- return i830_get_fence_size(pI830, size);
+ return i830_get_fence_size(intel, size);
}
static Bool
i830_check_display_stride(ScrnInfoPtr pScrn, int stride, Bool tiling)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
int limit = KB(32);
/* 8xx spec has always 8K limit, but tests show larger limit in
non-tiling mode, which makes large monitor work. */
- if ((IS_845G(pI830) || IS_I85X(pI830)) && tiling)
+ if ((IS_845G(intel) || IS_I85X(intel)) && tiling)
limit = KB(8);
- if (IS_I915(pI830) && tiling)
+ if (IS_I915(intel) && tiling)
limit = KB(8);
- if (IS_I965G(pI830) && tiling)
+ if (IS_I965G(intel) && tiling)
limit = KB(16);
if (stride <= limit)
@@ -181,10 +181,10 @@ void i830_free_memory(ScrnInfoPtr pScrn, i830_memory * mem)
return;
if (mem->bo != NULL) {
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
dri_bo_unreference(mem->bo);
- if (pI830->bo_list == mem) {
- pI830->bo_list = mem->next;
+ if (intel->bo_list == mem) {
+ intel->bo_list = mem->next;
if (mem->next)
mem->next->prev = NULL;
} else {
@@ -212,27 +212,27 @@ void i830_free_memory(ScrnInfoPtr pScrn, i830_memory * mem)
*/
void i830_reset_allocations(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
int p;
/* While there is any memory between the start and end markers, free it. */
- while (pI830->memory_list->next->next != NULL) {
- i830_memory *mem = pI830->memory_list->next;
+ while (intel->memory_list->next->next != NULL) {
+ i830_memory *mem = intel->memory_list->next;
i830_free_memory(pScrn, mem);
}
/* Free any allocations in buffer objects */
- while (pI830->bo_list != NULL)
- i830_free_memory(pScrn, pI830->bo_list);
+ while (intel->bo_list != NULL)
+ i830_free_memory(pScrn, intel->bo_list);
/* Null out the pointers for all the allocations we just freed. This is
* kind of gross, but at least it's just one place now.
*/
for (p = 0; p < 2; p++)
- pI830->cursor_mem_argb[p] = NULL;
+ intel->cursor_mem_argb[p] = NULL;
- pI830->front_buffer = NULL;
+ intel->front_buffer = NULL;
}
/**
@@ -246,7 +246,7 @@ void i830_reset_allocations(ScrnInfoPtr pScrn)
*/
Bool i830_allocator_init(ScrnInfoPtr pScrn, unsigned long size)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
i830_memory *start, *end;
start = xcalloc(1, sizeof(*start));
@@ -280,22 +280,22 @@ Bool i830_allocator_init(ScrnInfoPtr pScrn, unsigned long size)
end->size = 0;
end->prev = start;
- pI830->memory_list = start;
+ intel->memory_list = start;
return TRUE;
}
void i830_allocator_fini(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
/* Free most of the allocations */
i830_reset_allocations(pScrn);
/* Free the start/end markers */
- free(pI830->memory_list->next);
- free(pI830->memory_list);
- pI830->memory_list = NULL;
+ free(intel->memory_list->next);
+ free(intel->memory_list);
+ intel->memory_list = NULL;
}
static i830_memory *i830_allocate_memory_bo(ScrnInfoPtr pScrn, const char *name,
@@ -304,7 +304,7 @@ static i830_memory *i830_allocate_memory_bo(ScrnInfoPtr pScrn, const char *name,
unsigned long align, int flags,
enum tile_format tile_format)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
i830_memory *mem;
uint32_t bo_tiling_mode = I915_TILING_NONE;
int ret;
@@ -313,7 +313,7 @@ static i830_memory *i830_allocate_memory_bo(ScrnInfoPtr pScrn, const char *name,
/* Only allocate page-sized increments. */
size = ALIGN(size, GTT_PAGE_SIZE);
- align = i830_get_fence_alignment(pI830, size);
+ align = i830_get_fence_alignment(intel, size);
mem = xcalloc(1, sizeof(*mem));
if (mem == NULL)
@@ -325,7 +325,7 @@ static i830_memory *i830_allocate_memory_bo(ScrnInfoPtr pScrn, const char *name,
return NULL;
}
- mem->bo = dri_bo_alloc(pI830->bufmgr, name, size, align);
+ mem->bo = dri_bo_alloc(intel->bufmgr, name, size, align);
if (!mem->bo) {
xfree(mem->name);
@@ -369,10 +369,10 @@ static i830_memory *i830_allocate_memory_bo(ScrnInfoPtr pScrn, const char *name,
/* Insert new allocation into the list */
mem->prev = NULL;
- mem->next = pI830->bo_list;
- if (pI830->bo_list != NULL)
- pI830->bo_list->prev = mem;
- pI830->bo_list = mem;
+ mem->next = intel->bo_list;
+ if (intel->bo_list != NULL)
+ intel->bo_list->prev = mem;
+ intel->bo_list = mem;
return mem;
}
@@ -401,7 +401,7 @@ i830_memory *i830_allocate_memory(ScrnInfoPtr pScrn, const char *name,
enum tile_format tile_format)
{
i830_memory *mem;
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
/* Manage tile alignment and size constraints */
if (tile_format != TILE_NONE) {
@@ -409,7 +409,7 @@ i830_memory *i830_allocate_memory(ScrnInfoPtr pScrn, const char *name,
size = ALIGN(size, GTT_PAGE_SIZE);
/* Check for maximum tiled region size */
- if (IS_I9XX(pI830)) {
+ if (IS_I9XX(intel)) {
if (size > MB(128))
return NULL;
} else {
@@ -418,8 +418,8 @@ i830_memory *i830_allocate_memory(ScrnInfoPtr pScrn, const char *name,
}
/* round to size necessary for the fence register to work */
- size = i830_get_fence_size(pI830, size);
- alignment = i830_get_fence_alignment(pI830, size);
+ size = i830_get_fence_size(intel, size);
+ alignment = i830_get_fence_alignment(intel, size);
}
return i830_allocate_memory_bo(pScrn, name, size,
@@ -431,16 +431,16 @@ i830_memory *i830_allocate_memory(ScrnInfoPtr pScrn, const char *name,
void
i830_describe_allocations(ScrnInfoPtr pScrn, int verbosity, const char *prefix)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
i830_memory *mem;
- if (pI830->memory_list == NULL) {
+ if (intel->memory_list == NULL) {
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, verbosity,
"%sMemory allocator not initialized\n", prefix);
return;
}
- if (pI830->memory_list->next->next == NULL) {
+ if (intel->memory_list->next->next == NULL) {
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, verbosity,
"%sNo memory allocations\n", prefix);
return;
@@ -449,7 +449,7 @@ i830_describe_allocations(ScrnInfoPtr pScrn, int verbosity, const char *prefix)
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, verbosity,
"%sFixed memory allocation layout:\n", prefix);
- for (mem = pI830->memory_list->next; mem->next != NULL; mem = mem->next) {
+ for (mem = intel->memory_list->next; mem->next != NULL; mem = mem->next) {
char phys_suffix[32] = "";
char *tile_suffix = "";
@@ -465,11 +465,11 @@ i830_describe_allocations(ScrnInfoPtr pScrn, int verbosity, const char *prefix)
}
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, verbosity,
"%s0x%08lx: end of aperture\n",
- prefix, pI830->FbMapSize);
+ prefix, intel->FbMapSize);
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, verbosity,
"%sBO memory allocation layout:\n", prefix);
- for (mem = pI830->bo_list; mem != NULL; mem = mem->next) {
+ for (mem = intel->bo_list; mem != NULL; mem = mem->next) {
char *tile_suffix = "";
if (mem->tiling == TILE_XMAJOR)
@@ -485,9 +485,9 @@ i830_describe_allocations(ScrnInfoPtr pScrn, int verbosity, const char *prefix)
static Bool IsTileable(ScrnInfoPtr pScrn, int pitch)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
- if (IS_I965G(pI830)) {
+ if (IS_I965G(intel)) {
if (pitch / 512 * 512 == pitch && pitch <= KB(128))
return TRUE;
else
@@ -501,7 +501,7 @@ static Bool IsTileable(ScrnInfoPtr pScrn, int pitch)
switch (pitch) {
case 128:
case 256:
- if (IS_I945G(pI830) || IS_I945GM(pI830) || IS_G33CLASS(pI830))
+ if (IS_I945G(intel) || IS_I945GM(intel) || IS_G33CLASS(intel))
return TRUE;
else
return FALSE;
@@ -524,8 +524,8 @@ static Bool IsTileable(ScrnInfoPtr pScrn, int pitch)
*/
i830_memory *i830_allocate_framebuffer(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
- unsigned int pitch = pScrn->displayWidth * pI830->cpp;
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
+ unsigned int pitch = pScrn->displayWidth * intel->cpp;
unsigned long minspace;
int align;
long size, fb_height;
@@ -548,7 +548,7 @@ i830_memory *i830_allocate_framebuffer(ScrnInfoPtr pScrn)
size = ROUND_TO_PAGE(pitch * fb_height);
- if (pI830->tiling)
+ if (intel->tiling)
tile_format = TILE_XMAJOR;
if (!IsTileable(pScrn, pitch))
@@ -564,7 +564,7 @@ i830_memory *i830_allocate_framebuffer(ScrnInfoPtr pScrn)
/* Attempt to allocate it tiled first if we have page flipping on. */
if (tile_format != TILE_NONE) {
/* XXX: probably not the case on 965 */
- if (IS_I9XX(pI830))
+ if (IS_I9XX(intel))
align = MB(1);
else
align = KB(512);
@@ -586,7 +586,7 @@ i830_memory *i830_allocate_framebuffer(ScrnInfoPtr pScrn)
static Bool i830_allocate_cursor_buffers(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int i;
@@ -596,12 +596,12 @@ static Bool i830_allocate_cursor_buffers(ScrnInfoPtr pScrn)
* bail back to software cursors everywhere
*/
for (i = 0; i < xf86_config->num_crtc; i++) {
- pI830->cursor_mem_argb[i] =
+ intel->cursor_mem_argb[i] =
i830_allocate_memory(pScrn, "ARGB cursor",
HWCURSOR_SIZE_ARGB, PITCH_NONE,
GTT_PAGE_SIZE, DISABLE_REUSE,
TILE_NONE);
- if (!pI830->cursor_mem_argb[i])
+ if (!intel->cursor_mem_argb[i])
return FALSE;
}
@@ -614,7 +614,7 @@ static Bool i830_allocate_cursor_buffers(ScrnInfoPtr pScrn)
*/
Bool i830_allocate_2d_memory(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
/* Next, allocate other fixed-size allocations we have. */
if (!i830_allocate_cursor_buffers(pScrn)) {
@@ -623,8 +623,8 @@ Bool i830_allocate_2d_memory(ScrnInfoPtr pScrn)
return FALSE;
}
- pI830->front_buffer = i830_allocate_framebuffer(pScrn);
- if (pI830->front_buffer == NULL)
+ intel->front_buffer = i830_allocate_framebuffer(pScrn);
+ if (intel->front_buffer == NULL)
return FALSE;
return TRUE;
@@ -634,26 +634,26 @@ Bool i830_allocate_2d_memory(ScrnInfoPtr pScrn)
* Called at EnterVT to grab the AGP GART and bind our allocations.
*
* In zaphod mode, this will walk the list trying to bind twice, since each
- * pI830 points to the same allocation list, but the bind_memory will just
+ * intel points to the same allocation list, but the bind_memory will just
* no-op then.
*/
Bool i830_bind_all_memory(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
- if (pI830->memory_list == NULL)
+ if (intel->memory_list == NULL)
return TRUE;
int i;
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
for (i = 0; i < xf86_config->num_crtc; i++)
drmmode_crtc_set_cursor_bo(xf86_config->crtc[i],
- pI830->cursor_mem_argb[i]->bo);
+ intel->cursor_mem_argb[i]->bo);
i830_set_max_gtt_map_size(pScrn);
- if (pI830->front_buffer)
- pScrn->fbOffset = pI830->front_buffer->offset;
+ if (intel->front_buffer)
+ pScrn->fbOffset = intel->front_buffer->offset;
return TRUE;
}
@@ -701,21 +701,21 @@ void i830_free_xvmc_buffer(ScrnInfoPtr pScrn, i830_memory * buffer)
void i830_set_max_gtt_map_size(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
struct drm_i915_gem_get_aperture aperture;
int ret;
/* Default low value in case it gets used during server init. */
- pI830->max_gtt_map_size = 16 * 1024 * 1024;
+ intel->max_gtt_map_size = 16 * 1024 * 1024;
ret =
- ioctl(pI830->drmSubFD, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
+ ioctl(intel->drmSubFD, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
if (ret == 0) {
/* Let objects up get bound up to the size where only 2 would fit in
* the aperture, but then leave slop to account for alignment like
* libdrm does.
*/
- pI830->max_gtt_map_size =
+ intel->max_gtt_map_size =
aperture.aper_available_size * 3 / 4 / 2;
}
}
diff --git a/src/i830_render.c b/src/i830_render.c
index 4e849674..4969e0b6 100644
--- a/src/i830_render.c
+++ b/src/i830_render.c
@@ -271,17 +271,17 @@ static void i830_texture_setup(PicturePtr pPict, PixmapPtr pPix, int unit)
{
ScrnInfoPtr pScrn = xf86Screens[pPict->pDrawable->pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
uint32_t format, pitch, filter;
uint32_t wrap_mode;
uint32_t texcoordtype;
pitch = intel_get_pixmap_pitch(pPix);
- pI830->scale_units[unit][0] = pPix->drawable.width;
- pI830->scale_units[unit][1] = pPix->drawable.height;
- pI830->transform[unit] = pPict->transform;
+ intel->scale_units[unit][0] = pPix->drawable.width;
+ intel->scale_units[unit][1] = pPix->drawable.height;
+ intel->transform[unit] = pPict->transform;
- if (i830_transform_is_affine(pI830->transform[unit]))
+ if (i830_transform_is_affine(intel->transform[unit]))
texcoordtype = TEXCOORDTYPE_CARTESIAN;
else
texcoordtype = TEXCOORDTYPE_HOMOGENEOUS;
@@ -409,36 +409,36 @@ i830_prepare_composite(int op, PicturePtr pSrcPicture,
PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst)
{
ScrnInfoPtr pScrn = xf86Screens[pDstPicture->pDrawable->pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
- pI830->render_src_picture = pSrcPicture;
- pI830->render_src = pSrc;
- pI830->render_mask_picture = pMaskPicture;
- pI830->render_mask = pMask;
- pI830->render_dst_picture = pDstPicture;
- pI830->render_dst = pDst;
+ intel->render_src_picture = pSrcPicture;
+ intel->render_src = pSrc;
+ intel->render_mask_picture = pMaskPicture;
+ intel->render_mask = pMask;
+ intel->render_dst_picture = pDstPicture;
+ intel->render_dst = pDst;
i830_exa_check_pitch_3d(pSrc);
if (pMask)
i830_exa_check_pitch_3d(pMask);
i830_exa_check_pitch_3d(pDst);
- if (!i830_get_dest_format(pDstPicture, &pI830->render_dst_format))
+ if (!i830_get_dest_format(pDstPicture, &intel->render_dst_format))
return FALSE;
- pI830->dst_coord_adjust = 0;
- pI830->src_coord_adjust = 0;
- pI830->mask_coord_adjust = 0;
+ intel->dst_coord_adjust = 0;
+ intel->src_coord_adjust = 0;
+ intel->mask_coord_adjust = 0;
if (pSrcPicture->filter == PictFilterNearest)
- pI830->src_coord_adjust = 0.375;
+ intel->src_coord_adjust = 0.375;
if (pMask != NULL) {
- pI830->mask_coord_adjust = 0;
+ intel->mask_coord_adjust = 0;
if (pMaskPicture->filter == PictFilterNearest)
- pI830->mask_coord_adjust = 0.375;
+ intel->mask_coord_adjust = 0.375;
} else {
- pI830->transform[1] = NULL;
- pI830->scale_units[1][0] = -1;
- pI830->scale_units[1][1] = -1;
+ intel->transform[1] = NULL;
+ intel->scale_units[1][0] = -1;
+ intel->scale_units[1][1] = -1;
}
{
@@ -522,64 +522,64 @@ i830_prepare_composite(int op, PicturePtr pSrcPicture,
return FALSE;
}
- pI830->cblend = cblend;
- pI830->ablend = ablend;
- pI830->s8_blendctl = blendctl;
+ intel->cblend = cblend;
+ intel->ablend = ablend;
+ intel->s8_blendctl = blendctl;
}
i830_debug_sync(pScrn);
- pI830->needs_render_state_emit = TRUE;
+ intel->needs_render_state_emit = TRUE;
return TRUE;
}
static void i830_emit_composite_state(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
uint32_t vf2;
uint32_t texcoordfmt = 0;
- pI830->needs_render_state_emit = FALSE;
+ intel->needs_render_state_emit = FALSE;
IntelEmitInvarientState(pScrn);
- pI830->last_3d = LAST_3D_RENDER;
+ intel->last_3d = LAST_3D_RENDER;
BEGIN_BATCH(21);
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
OUT_BATCH(BUF_3D_ID_COLOR_BACK | BUF_3D_USE_FENCE |
- BUF_3D_PITCH(intel_get_pixmap_pitch(pI830->render_dst)));
- OUT_RELOC_PIXMAP(pI830->render_dst,
+ BUF_3D_PITCH(intel_get_pixmap_pitch(intel->render_dst)));
+ OUT_RELOC_PIXMAP(intel->render_dst,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
- OUT_BATCH(pI830->render_dst_format);
+ OUT_BATCH(intel->render_dst_format);
OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
OUT_BATCH(0);
OUT_BATCH(0); /* ymin, xmin */
- OUT_BATCH(DRAW_YMAX(pI830->render_dst->drawable.height - 1) |
- DRAW_XMAX(pI830->render_dst->drawable.width - 1));
+ OUT_BATCH(DRAW_YMAX(intel->render_dst->drawable.height - 1) |
+ DRAW_XMAX(intel->render_dst->drawable.width - 1));
OUT_BATCH(0); /* yorig, xorig */
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
I1_LOAD_S(2) | I1_LOAD_S(3) | I1_LOAD_S(8) | 2);
- if (pI830->render_mask)
+ if (intel->render_mask)
vf2 = 2 << 12; /* 2 texture coord sets */
else
vf2 = 1 << 12;
OUT_BATCH(vf2); /* number of coordinate sets */
OUT_BATCH(S3_CULLMODE_NONE | S3_VERTEXHAS_XY);
- OUT_BATCH(S8_ENABLE_COLOR_BLEND | S8_BLENDFUNC_ADD | pI830->
+ OUT_BATCH(S8_ENABLE_COLOR_BLEND | S8_BLENDFUNC_ADD | intel->
s8_blendctl | S8_ENABLE_COLOR_BUFFER_WRITE);
OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD | DISABLE_INDPT_ALPHA_BLEND);
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
LOAD_TEXTURE_BLEND_STAGE(0) | 1);
- OUT_BATCH(pI830->cblend);
- OUT_BATCH(pI830->ablend);
+ OUT_BATCH(intel->cblend);
+ OUT_BATCH(intel->ablend);
OUT_BATCH(_3DSTATE_ENABLES_1_CMD | DISABLE_LOGIC_OP |
DISABLE_STENCIL_TEST | DISABLE_DEPTH_BIAS |
@@ -590,13 +590,13 @@ static void i830_emit_composite_state(ScrnInfoPtr pScrn)
DISABLE_STENCIL_WRITE | ENABLE_TEX_CACHE |
DISABLE_DITHER | ENABLE_COLOR_WRITE | DISABLE_DEPTH_WRITE);
- if (i830_transform_is_affine(pI830->render_src_picture->transform))
+ if (i830_transform_is_affine(intel->render_src_picture->transform))
texcoordfmt |= (TEXCOORDFMT_2D << 0);
else
texcoordfmt |= (TEXCOORDFMT_3D << 0);
- if (pI830->render_mask) {
+ if (intel->render_mask) {
if (i830_transform_is_affine
- (pI830->render_mask_picture->transform))
+ (intel->render_mask_picture->transform))
texcoordfmt |= (TEXCOORDFMT_2D << 2);
else
texcoordfmt |= (TEXCOORDFMT_3D << 2);
@@ -605,10 +605,10 @@ static void i830_emit_composite_state(ScrnInfoPtr pScrn)
ADVANCE_BATCH();
- i830_texture_setup(pI830->render_src_picture, pI830->render_src, 0);
- if (pI830->render_mask) {
- i830_texture_setup(pI830->render_mask_picture,
- pI830->render_mask, 1);
+ i830_texture_setup(intel->render_src_picture, intel->render_src, 0);
+ if (intel->render_mask) {
+ i830_texture_setup(intel->render_mask_picture,
+ intel->render_mask, 1);
}
}
@@ -623,7 +623,7 @@ i830_emit_composite_primitive(PixmapPtr pDst,
int dstX, int dstY, int w, int h)
{
ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
Bool is_affine_src, is_affine_mask = TRUE;
int per_vertex, num_floats;
float src_x[3], src_y[3], src_w[3], mask_x[3], mask_y[3], mask_w[3];
@@ -631,27 +631,27 @@ i830_emit_composite_primitive(PixmapPtr pDst,
per_vertex = 2; /* dest x/y */
{
- float x = srcX + pI830->src_coord_adjust;
- float y = srcY + pI830->src_coord_adjust;
+ float x = srcX + intel->src_coord_adjust;
+ float y = srcY + intel->src_coord_adjust;
- is_affine_src = i830_transform_is_affine(pI830->transform[0]);
+ is_affine_src = i830_transform_is_affine(intel->transform[0]);
if (is_affine_src) {
if (!i830_get_transformed_coordinates(x, y,
- pI830->
+ intel->
transform[0],
&src_x[0],
&src_y[0]))
return;
if (!i830_get_transformed_coordinates(x, y + h,
- pI830->
+ intel->
transform[0],
&src_x[1],
&src_y[1]))
return;
if (!i830_get_transformed_coordinates(x + w, y + h,
- pI830->
+ intel->
transform[0],
&src_x[2],
&src_y[2]))
@@ -660,7 +660,7 @@ i830_emit_composite_primitive(PixmapPtr pDst,
per_vertex += 2; /* src x/y */
} else {
if (!i830_get_transformed_coordinates_3d(x, y,
- pI830->
+ intel->
transform[0],
&src_x[0],
&src_y[0],
@@ -668,7 +668,7 @@ i830_emit_composite_primitive(PixmapPtr pDst,
return;
if (!i830_get_transformed_coordinates_3d(x, y + h,
- pI830->
+ intel->
transform[0],
&src_x[1],
&src_y[1],
@@ -676,7 +676,7 @@ i830_emit_composite_primitive(PixmapPtr pDst,
return;
if (!i830_get_transformed_coordinates_3d(x + w, y + h,
- pI830->
+ intel->
transform[0],
&src_x[2],
&src_y[2],
@@ -687,28 +687,28 @@ i830_emit_composite_primitive(PixmapPtr pDst,
}
}
- if (pI830->render_mask) {
- float x = maskX + pI830->mask_coord_adjust;
- float y = maskY + pI830->mask_coord_adjust;
+ if (intel->render_mask) {
+ float x = maskX + intel->mask_coord_adjust;
+ float y = maskY + intel->mask_coord_adjust;
- is_affine_mask = i830_transform_is_affine(pI830->transform[1]);
+ is_affine_mask = i830_transform_is_affine(intel->transform[1]);
if (is_affine_mask) {
if (!i830_get_transformed_coordinates(x, y,
- pI830->
+ intel->
transform[1],
&mask_x[0],
&mask_y[0]))
return;
if (!i830_get_transformed_coordinates(x, y + h,
- pI830->
+ intel->
transform[1],
&mask_x[1],
&mask_y[1]))
return;
if (!i830_get_transformed_coordinates(x + w, y + h,
- pI830->
+ intel->
transform[1],
&mask_x[2],
&mask_y[2]))
@@ -717,7 +717,7 @@ i830_emit_composite_primitive(PixmapPtr pDst,
per_vertex += 2; /* mask x/y */
} else {
if (!i830_get_transformed_coordinates_3d(x, y,
- pI830->
+ intel->
transform[1],
&mask_x[0],
&mask_y[0],
@@ -725,7 +725,7 @@ i830_emit_composite_primitive(PixmapPtr pDst,
return;
if (!i830_get_transformed_coordinates_3d(x, y + h,
- pI830->
+ intel->
transform[1],
&mask_x[1],
&mask_y[1],
@@ -733,7 +733,7 @@ i830_emit_composite_primitive(PixmapPtr pDst,
return;
if (!i830_get_transformed_coordinates_3d(x + w, y + h,
- pI830->
+ intel->
transform[1],
&mask_x[2],
&mask_y[2],
@@ -749,46 +749,46 @@ i830_emit_composite_primitive(PixmapPtr pDst,
BEGIN_BATCH(1 + num_floats);
OUT_BATCH(PRIM3D_INLINE | PRIM3D_RECTLIST | (num_floats - 1));
- OUT_BATCH_F(pI830->dst_coord_adjust + dstX + w);
- OUT_BATCH_F(pI830->dst_coord_adjust + dstY + h);
- OUT_BATCH_F(src_x[2] / pI830->scale_units[0][0]);
- OUT_BATCH_F(src_y[2] / pI830->scale_units[0][1]);
+ OUT_BATCH_F(intel->dst_coord_adjust + dstX + w);
+ OUT_BATCH_F(intel->dst_coord_adjust + dstY + h);
+ OUT_BATCH_F(src_x[2] / intel->scale_units[0][0]);
+ OUT_BATCH_F(src_y[2] / intel->scale_units[0][1]);
if (!is_affine_src) {
OUT_BATCH_F(src_w[2]);
}
- if (pI830->render_mask) {
- OUT_BATCH_F(mask_x[2] / pI830->scale_units[1][0]);
- OUT_BATCH_F(mask_y[2] / pI830->scale_units[1][1]);
+ if (intel->render_mask) {
+ OUT_BATCH_F(mask_x[2] / intel->scale_units[1][0]);
+ OUT_BATCH_F(mask_y[2] / intel->scale_units[1][1]);
if (!is_affine_mask) {
OUT_BATCH_F(mask_w[2]);
}
}
- OUT_BATCH_F(pI830->dst_coord_adjust + dstX);
- OUT_BATCH_F(pI830->dst_coord_adjust + dstY + h);
- OUT_BATCH_F(src_x[1] / pI830->scale_units[0][0]);
- OUT_BATCH_F(src_y[1] / pI830->scale_units[0][1]);
+ OUT_BATCH_F(intel->dst_coord_adjust + dstX);
+ OUT_BATCH_F(intel->dst_coord_adjust + dstY + h);
+ OUT_BATCH_F(src_x[1] / intel->scale_units[0][0]);
+ OUT_BATCH_F(src_y[1] / intel->scale_units[0][1]);
if (!is_affine_src) {
OUT_BATCH_F(src_w[1]);
}
- if (pI830->render_mask) {
- OUT_BATCH_F(mask_x[1] / pI830->scale_units[1][0]);
- OUT_BATCH_F(mask_y[1] / pI830->scale_units[1][1]);
+ if (intel->render_mask) {
+ OUT_BATCH_F(mask_x[1] / intel->scale_units[1][0]);
+ OUT_BATCH_F(mask_y[1] / intel->scale_units[1][1]);
if (!is_affine_mask) {
OUT_BATCH_F(mask_w[1]);
}
}
- OUT_BATCH_F(pI830->dst_coord_adjust + dstX);
- OUT_BATCH_F(pI830->dst_coord_adjust + dstY);
- OUT_BATCH_F(src_x[0] / pI830->scale_units[0][0]);
- OUT_BATCH_F(src_y[0] / pI830->scale_units[0][1]);
+ OUT_BATCH_F(intel->dst_coord_adjust + dstX);
+ OUT_BATCH_F(intel->dst_coord_adjust + dstY);
+ OUT_BATCH_F(src_x[0] / intel->scale_units[0][0]);
+ OUT_BATCH_F(src_y[0] / intel->scale_units[0][1]);
if (!is_affine_src) {
OUT_BATCH_F(src_w[0]);
}
- if (pI830->render_mask) {
- OUT_BATCH_F(mask_x[0] / pI830->scale_units[1][0]);
- OUT_BATCH_F(mask_y[0] / pI830->scale_units[1][1]);
+ if (intel->render_mask) {
+ OUT_BATCH_F(mask_x[0] / intel->scale_units[1][0]);
+ OUT_BATCH_F(mask_y[0] / intel->scale_units[1][1]);
if (!is_affine_mask) {
OUT_BATCH_F(mask_w[0]);
}
@@ -805,14 +805,14 @@ i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
int dstX, int dstY, int w, int h)
{
ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
intel_batch_start_atomic(pScrn, 58 + /* invarient */
22 + /* setup */
20 + /* 2 * setup_texture */
1 + 30 /* verts */ );
- if (pI830->needs_render_state_emit)
+ if (intel->needs_render_state_emit)
i830_emit_composite_state(pScrn);
i830_emit_composite_primitive(pDst, srcX, srcY, maskX, maskY, dstX,
@@ -825,7 +825,7 @@ i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
void i830_batch_flush_notify(ScrnInfoPtr scrn)
{
- I830Ptr i830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
- i830->needs_render_state_emit = TRUE;
+ intel->needs_render_state_emit = TRUE;
}
diff --git a/src/i830_ring.h b/src/i830_ring.h
index 062b7ead..efa61c6c 100644
--- a/src/i830_ring.h
+++ b/src/i830_ring.h
@@ -33,13 +33,13 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define OUT_RING(n) do { \
if (I810_DEBUG & DEBUG_VERBOSE_RING) \
ErrorF("OUT_RING 0x%08x: 0x%08x, (mask %x)\n", \
- pI830->ring_next, (unsigned int)(n), \
- pI830->ring.tail_mask); \
- *(volatile uint32_t *)(pI830->ring.virtual_start + \
- pI830->ring_next) = n; \
- pI830->ring_used += 4; \
- pI830->ring_next += 4; \
- pI830->ring_next &= pI830->ring.tail_mask; \
+ intel->ring_next, (unsigned int)(n), \
+ intel->ring.tail_mask); \
+ *(volatile uint32_t *)(intel->ring.virtual_start + \
+ intel->ring_next) = n; \
+ intel->ring_used += 4; \
+ intel->ring_next += 4; \
+ intel->ring_next &= intel->ring.tail_mask; \
} while (0)
#define OUT_RING_F(x) do { \
@@ -49,43 +49,43 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
} while(0)
#define ADVANCE_LP_RING() do { \
- if (pI830->ring_emitting == 0) \
+ if (intel->ring_emitting == 0) \
FatalError("%s: ADVANCE_LP_RING called with no matching " \
"BEGIN_LP_RING\n", __FUNCTION__); \
- if (pI830->ring_used > pI830->ring_emitting) \
+ if (intel->ring_used > intel->ring_emitting) \
FatalError("%s: ADVANCE_LP_RING: exceeded allocation %d/%d\n ", \
- __FUNCTION__, pI830->ring_used, \
- pI830->ring_emitting); \
- if (pI830->ring_used < pI830->ring_emitting) \
+ __FUNCTION__, intel->ring_used, \
+ intel->ring_emitting); \
+ if (intel->ring_used < intel->ring_emitting) \
FatalError("%s: ADVANCE_LP_RING: under-used allocation %d/%d\n ", \
- __FUNCTION__, pI830->ring_used, \
- pI830->ring_emitting); \
- pI830->ring.tail = pI830->ring_next; \
- pI830->ring.space -= pI830->ring_used; \
- if (pI830->ring_next & 0x07) \
+ __FUNCTION__, intel->ring_used, \
+ intel->ring_emitting); \
+ intel->ring.tail = intel->ring_next; \
+ intel->ring.space -= intel->ring_used; \
+ if (intel->ring_next & 0x07) \
FatalError("%s: ADVANCE_LP_RING: " \
"ring_next (0x%x) isn't on a QWord boundary\n", \
- __FUNCTION__, pI830->ring_next); \
- OUTREG(LP_RING + RING_TAIL, pI830->ring_next); \
- pI830->ring_emitting = 0; \
+ __FUNCTION__, intel->ring_next); \
+ OUTREG(LP_RING + RING_TAIL, intel->ring_next); \
+ intel->ring_emitting = 0; \
} while (0)
#define BEGIN_LP_RING(n) \
do { \
- if (pI830->ring_emitting != 0) \
+ if (intel->ring_emitting != 0) \
FatalError("%s: BEGIN_LP_RING called without closing " \
"ADVANCE_LP_RING\n", __FUNCTION__); \
if ((n) > 2 && (I810_DEBUG&DEBUG_ALWAYS_SYNC)) \
i830_wait_ring_idle(pScrn); \
- pI830->ring_emitting = (n) * 4; \
+ intel->ring_emitting = (n) * 4; \
if ((n) & 1) \
- pI830->ring_emitting += 4; \
- if (pI830->ring.space < pI830->ring_emitting) \
- WaitRingFunc(pScrn, pI830->ring_emitting, 0); \
- pI830->ring_next = pI830->ring.tail; \
+ intel->ring_emitting += 4; \
+ if (intel->ring.space < intel->ring_emitting) \
+ WaitRingFunc(pScrn, intel->ring_emitting, 0); \
+ intel->ring_next = intel->ring.tail; \
if (I810_DEBUG & DEBUG_VERBOSE_RING) \
ErrorF( "BEGIN_LP_RING %d in %s\n", n, FUNCTION_NAME); \
- pI830->ring_used = 0; \
+ intel->ring_used = 0; \
if ((n) & 1) \
OUT_RING(MI_NOOP); \
} while (0)
diff --git a/src/i830_uxa.c b/src/i830_uxa.c
index ecd654e3..f28731f9 100644
--- a/src/i830_uxa.c
+++ b/src/i830_uxa.c
@@ -108,15 +108,15 @@ Bool
i830_get_aperture_space(ScrnInfoPtr pScrn, drm_intel_bo ** bo_table,
int num_bos)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
- if (pI830->batch_bo == NULL)
+ if (intel->batch_bo == NULL)
I830FALLBACK("VT inactive\n");
- bo_table[0] = pI830->batch_bo;
+ bo_table[0] = intel->batch_bo;
if (drm_intel_bufmgr_check_aperture_space(bo_table, num_bos) != 0) {
intel_batch_flush(pScrn, FALSE);
- bo_table[0] = pI830->batch_bo;
+ bo_table[0] = intel->batch_bo;
if (drm_intel_bufmgr_check_aperture_space(bo_table, num_bos) !=
0)
I830FALLBACK("Couldn't get aperture space for BOs\n");
@@ -132,10 +132,10 @@ static unsigned long i830_pixmap_pitch(PixmapPtr pixmap)
static int i830_pixmap_pitch_is_aligned(PixmapPtr pixmap)
{
ScrnInfoPtr pScrn = xf86Screens[pixmap->drawable.pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
return i830_pixmap_pitch(pixmap) %
- pI830->accel_pixmap_pitch_alignment == 0;
+ intel->accel_pixmap_pitch_alignment == 0;
}
/**
@@ -145,7 +145,7 @@ static Bool
i830_uxa_prepare_solid(PixmapPtr pPixmap, int alu, Pixel planemask, Pixel fg)
{
ScrnInfoPtr pScrn = xf86Screens[pPixmap->drawable.pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
unsigned long pitch;
drm_intel_bo *bo_table[] = {
NULL, /* batch_bo */
@@ -171,27 +171,27 @@ i830_uxa_prepare_solid(PixmapPtr pPixmap, int alu, Pixel planemask, Pixel fg)
if (!i830_get_aperture_space(pScrn, bo_table, ARRAY_SIZE(bo_table)))
return FALSE;
- pI830->BR[13] = (I830PatternROP[alu] & 0xff) << 16;
+ intel->BR[13] = (I830PatternROP[alu] & 0xff) << 16;
switch (pPixmap->drawable.bitsPerPixel) {
case 8:
break;
case 16:
/* RGB565 */
- pI830->BR[13] |= (1 << 24);
+ intel->BR[13] |= (1 << 24);
break;
case 32:
/* RGB8888 */
- pI830->BR[13] |= ((1 << 24) | (1 << 25));
+ intel->BR[13] |= ((1 << 24) | (1 << 25));
break;
}
- pI830->BR[16] = fg;
+ intel->BR[16] = fg;
return TRUE;
}
static void i830_uxa_solid(PixmapPtr pPixmap, int x1, int y1, int x2, int y2)
{
ScrnInfoPtr pScrn = xf86Screens[pPixmap->drawable.pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
unsigned long pitch;
uint32_t cmd;
@@ -206,7 +206,7 @@ static void i830_uxa_solid(PixmapPtr pPixmap, int x1, int y1, int x2, int y2)
cmd |=
XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB;
- if (IS_I965G(pI830) && i830_pixmap_tiled(pPixmap)) {
+ if (IS_I965G(intel) && i830_pixmap_tiled(pPixmap)) {
assert((pitch % 512) == 0);
pitch >>= 2;
cmd |= XY_COLOR_BLT_TILED;
@@ -214,12 +214,12 @@ static void i830_uxa_solid(PixmapPtr pPixmap, int x1, int y1, int x2, int y2)
OUT_BATCH(cmd);
- OUT_BATCH(pI830->BR[13] | pitch);
+ OUT_BATCH(intel->BR[13] | pitch);
OUT_BATCH((y1 << 16) | (x1 & 0xffff));
OUT_BATCH((y2 << 16) | (x2 & 0xffff));
OUT_RELOC_PIXMAP(pPixmap, I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER, 0);
- OUT_BATCH(pI830->BR[16]);
+ OUT_BATCH(intel->BR[16]);
ADVANCE_BATCH();
}
}
@@ -240,7 +240,7 @@ i830_uxa_prepare_copy(PixmapPtr pSrcPixmap, PixmapPtr pDstPixmap, int xdir,
int ydir, int alu, Pixel planemask)
{
ScrnInfoPtr pScrn = xf86Screens[pDstPixmap->drawable.pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
drm_intel_bo *bo_table[] = {
NULL, /* batch_bo */
i830_get_pixmap_bo(pSrcPixmap),
@@ -259,18 +259,18 @@ i830_uxa_prepare_copy(PixmapPtr pSrcPixmap, PixmapPtr pDstPixmap, int xdir,
i830_exa_check_pitch_2d(pSrcPixmap);
i830_exa_check_pitch_2d(pDstPixmap);
- pI830->pSrcPixmap = pSrcPixmap;
+ intel->pSrcPixmap = pSrcPixmap;
- pI830->BR[13] = I830CopyROP[alu] << 16;
+ intel->BR[13] = I830CopyROP[alu] << 16;
switch (pSrcPixmap->drawable.bitsPerPixel) {
case 8:
break;
case 16:
- pI830->BR[13] |= (1 << 24);
+ intel->BR[13] |= (1 << 24);
break;
case 32:
- pI830->BR[13] |= ((1 << 25) | (1 << 24));
+ intel->BR[13] |= ((1 << 25) | (1 << 24));
break;
}
return TRUE;
@@ -281,7 +281,7 @@ i830_uxa_copy(PixmapPtr pDstPixmap, int src_x1, int src_y1, int dst_x1,
int dst_y1, int w, int h)
{
ScrnInfoPtr pScrn = xf86Screens[pDstPixmap->drawable.pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
uint32_t cmd;
int dst_x2, dst_y2;
unsigned int dst_pitch, src_pitch;
@@ -290,7 +290,7 @@ i830_uxa_copy(PixmapPtr pDstPixmap, int src_x1, int src_y1, int dst_x1,
dst_y2 = dst_y1 + h;
dst_pitch = i830_pixmap_pitch(pDstPixmap);
- src_pitch = i830_pixmap_pitch(pI830->pSrcPixmap);
+ src_pitch = i830_pixmap_pitch(intel->pSrcPixmap);
{
BEGIN_BATCH(8);
@@ -302,14 +302,14 @@ i830_uxa_copy(PixmapPtr pDstPixmap, int src_x1, int src_y1, int dst_x1,
XY_SRC_COPY_BLT_WRITE_ALPHA |
XY_SRC_COPY_BLT_WRITE_RGB;
- if (IS_I965G(pI830)) {
+ if (IS_I965G(intel)) {
if (i830_pixmap_tiled(pDstPixmap)) {
assert((dst_pitch % 512) == 0);
dst_pitch >>= 2;
cmd |= XY_SRC_COPY_BLT_DST_TILED;
}
- if (i830_pixmap_tiled(pI830->pSrcPixmap)) {
+ if (i830_pixmap_tiled(intel->pSrcPixmap)) {
assert((src_pitch % 512) == 0);
src_pitch >>= 2;
cmd |= XY_SRC_COPY_BLT_SRC_TILED;
@@ -318,14 +318,14 @@ i830_uxa_copy(PixmapPtr pDstPixmap, int src_x1, int src_y1, int dst_x1,
OUT_BATCH(cmd);
- OUT_BATCH(pI830->BR[13] | dst_pitch);
+ OUT_BATCH(intel->BR[13] | dst_pitch);
OUT_BATCH((dst_y1 << 16) | (dst_x1 & 0xffff));
OUT_BATCH((dst_y2 << 16) | (dst_x2 & 0xffff));
OUT_RELOC_PIXMAP(pDstPixmap, I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH((src_y1 << 16) | (src_x1 & 0xffff));
OUT_BATCH(src_pitch);
- OUT_RELOC_PIXMAP(pI830->pSrcPixmap, I915_GEM_DOMAIN_RENDER, 0,
+ OUT_RELOC_PIXMAP(intel->pSrcPixmap, I915_GEM_DOMAIN_RENDER, 0,
0);
ADVANCE_BATCH();
@@ -457,7 +457,7 @@ static Bool i830_uxa_prepare_access(PixmapPtr pixmap, uxa_access_t access)
{
dri_bo *bo = i830_get_pixmap_bo(pixmap);
ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum];
- I830Ptr i830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
intel_batch_flush(scrn, FALSE);
@@ -470,7 +470,7 @@ static Bool i830_uxa_prepare_access(PixmapPtr pixmap, uxa_access_t access)
}
/* Kernel manages fences at GTT map/fault time */
- if (bo->size < i830->max_gtt_map_size) {
+ if (bo->size < intel->max_gtt_map_size) {
if (drm_intel_gem_bo_map_gtt(bo)) {
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
"%s: bo map failed\n", __FUNCTION__);
@@ -495,10 +495,10 @@ static void i830_uxa_finish_access(PixmapPtr pixmap)
if (bo) {
ScreenPtr screen = pixmap->drawable.pScreen;
ScrnInfoPtr scrn = xf86Screens[screen->myNum];
- I830Ptr i830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
- if (bo == i830->front_buffer->bo)
- i830->need_flush = TRUE;
+ if (bo == intel->front_buffer->bo)
+ intel->need_flush = TRUE;
if (!scrn->vtSema) {
dri_bo_unmap(bo);
@@ -506,7 +506,7 @@ static void i830_uxa_finish_access(PixmapPtr pixmap)
return;
}
- if (bo->size < i830->max_gtt_map_size)
+ if (bo->size < intel->max_gtt_map_size)
drm_intel_gem_bo_unmap_gtt(bo);
else
dri_bo_unmap(bo);
@@ -517,11 +517,11 @@ static void i830_uxa_finish_access(PixmapPtr pixmap)
void i830_uxa_block_handler(ScreenPtr screen)
{
ScrnInfoPtr scrn = xf86Screens[screen->myNum];
- I830Ptr i830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
- if (i830->need_flush) {
- dri_bo_wait_rendering(i830->front_buffer->bo);
- i830->need_flush = FALSE;
+ if (intel->need_flush) {
+ dri_bo_wait_rendering(intel->front_buffer->bo);
+ intel->need_flush = FALSE;
}
}
@@ -541,7 +541,7 @@ i830_uxa_create_pixmap(ScreenPtr screen, int w, int h, int depth,
unsigned usage)
{
ScrnInfoPtr scrn = xf86Screens[screen->myNum];
- I830Ptr i830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
dri_bo *bo;
int stride;
PixmapPtr pixmap;
@@ -566,7 +566,7 @@ i830_uxa_create_pixmap(ScreenPtr screen, int w, int h, int depth,
tiling = I915_TILING_Y;
pitch_align = 512;
} else {
- pitch_align = i830->accel_pixmap_pitch_alignment;
+ pitch_align = intel->accel_pixmap_pitch_alignment;
}
stride = ROUND_TO((w * pixmap->drawable.bitsPerPixel + 7) / 8,
@@ -585,14 +585,14 @@ i830_uxa_create_pixmap(ScreenPtr screen, int w, int h, int depth,
else
aligned_h = ALIGN(h, 32);
- stride = i830_get_fence_pitch(i830, stride, tiling);
+ stride = i830_get_fence_pitch(intel, stride, tiling);
/* Round the object up to the size of the fence it will live in
* if necessary. We could potentially make the kernel allocate
* a larger aperture space and just bind the subset of pages in,
* but this is easier and also keeps us out of trouble (as much)
* with drm_intel_bufmgr_check_aperture().
*/
- size = i830_get_fence_size(i830, stride * aligned_h);
+ size = i830_get_fence_size(intel, stride * aligned_h);
assert(size >= stride * aligned_h);
}
@@ -611,10 +611,10 @@ i830_uxa_create_pixmap(ScreenPtr screen, int w, int h, int depth,
}
if (usage == UXA_CREATE_PIXMAP_FOR_MAP)
- bo = drm_intel_bo_alloc(i830->bufmgr, "pixmap", size,
+ bo = drm_intel_bo_alloc(intel->bufmgr, "pixmap", size,
0);
else
- bo = drm_intel_bo_alloc_for_render(i830->bufmgr,
+ bo = drm_intel_bo_alloc_for_render(intel->bufmgr,
"pixmap", size, 0);
if (!bo) {
fbDestroyPixmap(pixmap);
@@ -647,8 +647,8 @@ static Bool i830_uxa_destroy_pixmap(PixmapPtr pixmap)
void i830_uxa_create_screen_resources(ScreenPtr pScreen)
{
ScrnInfoPtr scrn = xf86Screens[pScreen->myNum];
- I830Ptr i830 = I830PTR(scrn);
- dri_bo *bo = i830->front_buffer->bo;
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+ dri_bo *bo = intel->front_buffer->bo;
if (bo != NULL) {
PixmapPtr pixmap = pScreen->GetScreenPixmap(pScreen);
@@ -660,65 +660,65 @@ void i830_uxa_create_screen_resources(ScreenPtr pScreen)
Bool i830_uxa_init(ScreenPtr pScreen)
{
ScrnInfoPtr scrn = xf86Screens[pScreen->myNum];
- I830Ptr i830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
if (!dixRequestPrivate(&uxa_pixmap_index, 0))
return FALSE;
- i830->uxa_driver = uxa_driver_alloc();
- if (i830->uxa_driver == NULL)
+ intel->uxa_driver = uxa_driver_alloc();
+ if (intel->uxa_driver == NULL)
return FALSE;
- memset(i830->uxa_driver, 0, sizeof(*i830->uxa_driver));
+ memset(intel->uxa_driver, 0, sizeof(*intel->uxa_driver));
- i830->bufferOffset = 0;
- i830->uxa_driver->uxa_major = 1;
- i830->uxa_driver->uxa_minor = 0;
+ intel->bufferOffset = 0;
+ intel->uxa_driver->uxa_major = 1;
+ intel->uxa_driver->uxa_minor = 0;
/* Solid fill */
- i830->uxa_driver->prepare_solid = i830_uxa_prepare_solid;
- i830->uxa_driver->solid = i830_uxa_solid;
- i830->uxa_driver->done_solid = i830_uxa_done_solid;
+ intel->uxa_driver->prepare_solid = i830_uxa_prepare_solid;
+ intel->uxa_driver->solid = i830_uxa_solid;
+ intel->uxa_driver->done_solid = i830_uxa_done_solid;
/* Copy */
- i830->uxa_driver->prepare_copy = i830_uxa_prepare_copy;
- i830->uxa_driver->copy = i830_uxa_copy;
- i830->uxa_driver->done_copy = i830_uxa_done_copy;
+ intel->uxa_driver->prepare_copy = i830_uxa_prepare_copy;
+ intel->uxa_driver->copy = i830_uxa_copy;
+ intel->uxa_driver->done_copy = i830_uxa_done_copy;
/* Composite */
- if (!IS_I9XX(i830)) {
- i830->uxa_driver->check_composite = i830_check_composite;
- i830->uxa_driver->prepare_composite = i830_prepare_composite;
- i830->uxa_driver->composite = i830_composite;
- i830->uxa_driver->done_composite = i830_done_composite;
- } else if (IS_I915G(i830) || IS_I915GM(i830) ||
- IS_I945G(i830) || IS_I945GM(i830) || IS_G33CLASS(i830)) {
- i830->uxa_driver->check_composite = i915_check_composite;
- i830->uxa_driver->prepare_composite = i915_prepare_composite;
- i830->uxa_driver->composite = i915_composite;
- i830->uxa_driver->done_composite = i830_done_composite;
+ if (!IS_I9XX(intel)) {
+ intel->uxa_driver->check_composite = i830_check_composite;
+ intel->uxa_driver->prepare_composite = i830_prepare_composite;
+ intel->uxa_driver->composite = i830_composite;
+ intel->uxa_driver->done_composite = i830_done_composite;
+ } else if (IS_I915G(intel) || IS_I915GM(intel) ||
+ IS_I945G(intel) || IS_I945GM(intel) || IS_G33CLASS(intel)) {
+ intel->uxa_driver->check_composite = i915_check_composite;
+ intel->uxa_driver->prepare_composite = i915_prepare_composite;
+ intel->uxa_driver->composite = i915_composite;
+ intel->uxa_driver->done_composite = i830_done_composite;
} else {
- i830->uxa_driver->check_composite = i965_check_composite;
- i830->uxa_driver->prepare_composite = i965_prepare_composite;
- i830->uxa_driver->composite = i965_composite;
- i830->uxa_driver->done_composite = i830_done_composite;
+ intel->uxa_driver->check_composite = i965_check_composite;
+ intel->uxa_driver->prepare_composite = i965_prepare_composite;
+ intel->uxa_driver->composite = i965_composite;
+ intel->uxa_driver->done_composite = i830_done_composite;
}
- i830->uxa_driver->prepare_access = i830_uxa_prepare_access;
- i830->uxa_driver->finish_access = i830_uxa_finish_access;
- i830->uxa_driver->pixmap_is_offscreen = i830_uxa_pixmap_is_offscreen;
+ intel->uxa_driver->prepare_access = i830_uxa_prepare_access;
+ intel->uxa_driver->finish_access = i830_uxa_finish_access;
+ intel->uxa_driver->pixmap_is_offscreen = i830_uxa_pixmap_is_offscreen;
- if (!uxa_driver_init(pScreen, i830->uxa_driver)) {
+ if (!uxa_driver_init(pScreen, intel->uxa_driver)) {
xf86DrvMsg(scrn->scrnIndex, X_ERROR,
"UXA initialization failed\n");
- xfree(i830->uxa_driver);
+ xfree(intel->uxa_driver);
return FALSE;
}
pScreen->CreatePixmap = i830_uxa_create_pixmap;
pScreen->DestroyPixmap = i830_uxa_destroy_pixmap;
- uxa_set_fallback_debug(pScreen, i830->fallback_debug);
+ uxa_set_fallback_debug(pScreen, intel->fallback_debug);
return TRUE;
}
diff --git a/src/i830_video.c b/src/i830_video.c
index 820c2d82..1667ca0b 100644
--- a/src/i830_video.c
+++ b/src/i830_video.c
@@ -205,7 +205,7 @@ static XF86ImageRec Images[NUM_IMAGES] = {
};
#if VIDEO_DEBUG
-static void CompareOverlay(I830Ptr pI830, uint32_t * overlay, int size)
+static void CompareOverlay(intel_screen_private *intel, uint32_t * overlay, int size)
{
int i;
uint32_t val;
@@ -229,7 +229,7 @@ static void CompareOverlay(I830Ptr pI830, uint32_t * overlay, int size)
static Bool drmmode_has_overlay(ScrnInfoPtr pScrn)
{
#ifdef DRM_MODE_OVERLAY_LANDED
- I830Ptr p830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
struct drm_i915_getparam gp;
int has_overlay = 0;
@@ -246,7 +246,7 @@ static Bool drmmode_has_overlay(ScrnInfoPtr pScrn)
static void drmmode_overlay_update_attrs(ScrnInfoPtr pScrn)
{
#ifdef DRM_MODE_OVERLAY_LANDED
- I830Ptr p830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
I830PortPrivPtr pPriv = GET_PORT_PRIVATE(pScrn);
struct drm_intel_overlay_attrs attrs;
int ret;
@@ -274,7 +274,7 @@ static void drmmode_overlay_update_attrs(ScrnInfoPtr pScrn)
static void drmmode_overlay_off(ScrnInfoPtr pScrn)
{
#ifdef DRM_MODE_OVERLAY_LANDED
- I830Ptr p830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
struct drm_intel_overlay_put_image request;
int ret;
@@ -296,7 +296,7 @@ drmmode_overlay_put_image(ScrnInfoPtr pScrn, xf86CrtcPtr crtc,
short drw_h)
{
#ifdef DRM_MODE_OVERLAY_LANDED
- I830Ptr p830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
I830PortPrivPtr pPriv = GET_PORT_PRIVATE(pScrn);
struct drm_intel_overlay_put_image request;
int ret;
@@ -369,7 +369,7 @@ drmmode_overlay_put_image(ScrnInfoPtr pScrn, xf86CrtcPtr crtc,
void I830InitVideo(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
XF86VideoAdaptorPtr *adaptors, *newAdaptors = NULL;
XF86VideoAdaptorPtr overlayAdaptor = NULL, texturedAdaptor = NULL;
int num_adaptors;
@@ -399,8 +399,8 @@ void I830InitVideo(ScreenPtr pScreen)
/* Set up textured video if we can do it at this depth and we are on
* supported hardware.
*/
- if (pScrn->bitsPerPixel >= 16 && (IS_I9XX(pI830) || IS_I965G(pI830)) &&
- !(!IS_I965G(pI830) && pScrn->displayWidth > 2048)) {
+ if (pScrn->bitsPerPixel >= 16 && (IS_I9XX(intel) || IS_I965G(intel)) &&
+ !(!IS_I965G(intel) && pScrn->displayWidth > 2048)) {
texturedAdaptor = I830SetupImageVideoTextured(pScreen);
if (texturedAdaptor != NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@@ -412,9 +412,9 @@ void I830InitVideo(ScreenPtr pScreen)
}
/* Set up overlay video if we can do it at this depth. */
- if (!OVERLAY_NOEXIST(pI830) && pScrn->bitsPerPixel != 8) {
- pI830->use_drmmode_overlay = drmmode_has_overlay(pScrn);
- if (pI830->use_drmmode_overlay) {
+ if (!OVERLAY_NOEXIST(intel) && pScrn->bitsPerPixel != 8) {
+ intel->use_drmmode_overlay = drmmode_has_overlay(pScrn);
+ if (intel->use_drmmode_overlay) {
overlayAdaptor = I830SetupImageVideoOverlay(pScreen);
if (overlayAdaptor != NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@@ -426,13 +426,13 @@ void I830InitVideo(ScreenPtr pScreen)
}
}
- if (overlayAdaptor && pI830->XvPreferOverlay)
+ if (overlayAdaptor && intel->XvPreferOverlay)
adaptors[num_adaptors++] = overlayAdaptor;
if (texturedAdaptor)
adaptors[num_adaptors++] = texturedAdaptor;
- if (overlayAdaptor && !pI830->XvPreferOverlay)
+ if (overlayAdaptor && !intel->XvPreferOverlay)
adaptors[num_adaptors++] = overlayAdaptor;
#ifdef INTEL_XVMC
@@ -448,7 +448,7 @@ void I830InitVideo(ScreenPtr pScreen)
} else {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Disabling Xv because no adaptors could be initialized.\n");
- pI830->XvEnabled = FALSE;
+ intel->XvEnabled = FALSE;
}
#ifdef INTEL_XVMC
@@ -467,7 +467,7 @@ void I830InitVideo(ScreenPtr pScreen)
static XF86VideoAdaptorPtr I830SetupImageVideoOverlay(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
XF86VideoAdaptorPtr adapt;
I830PortPrivPtr pPriv;
XF86AttributePtr att;
@@ -484,7 +484,7 @@ static XF86VideoAdaptorPtr I830SetupImageVideoOverlay(ScreenPtr pScreen)
adapt->nEncodings = 1;
adapt->pEncodings = DummyEncoding;
/* update the DummyEncoding for these two chipsets */
- if (IS_845G(pI830) || IS_I830(pI830)) {
+ if (IS_845G(intel) || IS_I830(intel)) {
adapt->pEncodings->width = IMAGE_MAX_WIDTH_LEGACY;
adapt->pEncodings->height = IMAGE_MAX_HEIGHT_LEGACY;
}
@@ -498,7 +498,7 @@ static XF86VideoAdaptorPtr I830SetupImageVideoOverlay(ScreenPtr pScreen)
adapt->pPortPrivates[0].ptr = (pointer) (pPriv);
adapt->nAttributes = NUM_ATTRIBUTES;
adapt->nAttributes += CLONE_ATTRIBUTES;
- if (IS_I9XX(pI830))
+ if (IS_I9XX(intel))
adapt->nAttributes += GAMMA_ATTRIBUTES; /* has gamma */
adapt->pAttributes =
xnfalloc(sizeof(XF86AttributeRec) * adapt->nAttributes);
@@ -510,7 +510,7 @@ static XF86VideoAdaptorPtr I830SetupImageVideoOverlay(ScreenPtr pScreen)
memcpy((char *)att, (char *)CloneAttributes,
sizeof(XF86AttributeRec) * CLONE_ATTRIBUTES);
att += CLONE_ATTRIBUTES;
- if (IS_I9XX(pI830)) {
+ if (IS_I9XX(intel)) {
memcpy((char *)att, (char *)GammaAttributes,
sizeof(XF86AttributeRec) * GAMMA_ATTRIBUTES);
att += GAMMA_ATTRIBUTES;
@@ -529,7 +529,7 @@ static XF86VideoAdaptorPtr I830SetupImageVideoOverlay(ScreenPtr pScreen)
adapt->QueryImageAttributes = I830QueryImageAttributes;
pPriv->textured = FALSE;
- pPriv->colorKey = pI830->colorKey & ((1 << pScrn->depth) - 1);
+ pPriv->colorKey = intel->colorKey & ((1 << pScrn->depth) - 1);
pPriv->videoStatus = 0;
pPriv->brightness = -19; /* (255/219) * -16 */
pPriv->contrast = 75; /* 255/219 * 64 */
@@ -551,7 +551,7 @@ static XF86VideoAdaptorPtr I830SetupImageVideoOverlay(ScreenPtr pScreen)
/* gotta uninit this someplace */
REGION_NULL(pScreen, &pPriv->clip);
- pI830->adaptor = adapt;
+ intel->adaptor = adapt;
/* With LFP's we need to detect whether we're in One Line Mode, which
* essentially means a resolution greater than 1024x768, and fix up
@@ -574,7 +574,7 @@ static XF86VideoAdaptorPtr I830SetupImageVideoOverlay(ScreenPtr pScreen)
/* Allow the pipe to be switched from pipe A to B when in clone mode */
xvPipe = MAKE_ATOM("XV_PIPE");
- if (IS_I9XX(pI830)) {
+ if (IS_I9XX(intel)) {
xvGamma0 = MAKE_ATOM("XV_GAMMA0");
xvGamma1 = MAKE_ATOM("XV_GAMMA1");
xvGamma2 = MAKE_ATOM("XV_GAMMA2");
@@ -736,7 +736,7 @@ I830SetPortAttributeOverlay(ScrnInfoPtr pScrn,
Atom attribute, INT32 value, pointer data)
{
I830PortPrivPtr pPriv = (I830PortPrivPtr) data;
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
if (attribute == xvBrightness) {
if ((value < -128) || (value > 127))
@@ -763,17 +763,17 @@ I830SetPortAttributeOverlay(ScrnInfoPtr pScrn,
/*
* Leave this to be updated at the next frame
*/
- } else if (attribute == xvGamma0 && (IS_I9XX(pI830))) {
+ } else if (attribute == xvGamma0 && (IS_I9XX(intel))) {
pPriv->gamma0 = value;
- } else if (attribute == xvGamma1 && (IS_I9XX(pI830))) {
+ } else if (attribute == xvGamma1 && (IS_I9XX(intel))) {
pPriv->gamma1 = value;
- } else if (attribute == xvGamma2 && (IS_I9XX(pI830))) {
+ } else if (attribute == xvGamma2 && (IS_I9XX(intel))) {
pPriv->gamma2 = value;
- } else if (attribute == xvGamma3 && (IS_I9XX(pI830))) {
+ } else if (attribute == xvGamma3 && (IS_I9XX(intel))) {
pPriv->gamma3 = value;
- } else if (attribute == xvGamma4 && (IS_I9XX(pI830))) {
+ } else if (attribute == xvGamma4 && (IS_I9XX(intel))) {
pPriv->gamma4 = value;
- } else if (attribute == xvGamma5 && (IS_I9XX(pI830))) {
+ } else if (attribute == xvGamma5 && (IS_I9XX(intel))) {
pPriv->gamma5 = value;
} else if (attribute == xvColorKey) {
pPriv->colorKey = value;
@@ -787,7 +787,7 @@ I830SetPortAttributeOverlay(ScrnInfoPtr pScrn,
attribute == xvGamma2 ||
attribute == xvGamma3 ||
attribute == xvGamma4 ||
- attribute == xvGamma5) && (IS_I9XX(pI830))) {
+ attribute == xvGamma5) && (IS_I9XX(intel))) {
OVERLAY_DEBUG("GAMMA\n");
}
@@ -803,7 +803,7 @@ static int
I830GetPortAttribute(ScrnInfoPtr pScrn,
Atom attribute, INT32 * value, pointer data)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
I830PortPrivPtr pPriv = (I830PortPrivPtr) data;
if (attribute == xvBrightness) {
@@ -821,17 +821,17 @@ I830GetPortAttribute(ScrnInfoPtr pScrn,
if (c == xf86_config->num_crtc)
c = -1;
*value = c;
- } else if (attribute == xvGamma0 && (IS_I9XX(pI830))) {
+ } else if (attribute == xvGamma0 && (IS_I9XX(intel))) {
*value = pPriv->gamma0;
- } else if (attribute == xvGamma1 && (IS_I9XX(pI830))) {
+ } else if (attribute == xvGamma1 && (IS_I9XX(intel))) {
*value = pPriv->gamma1;
- } else if (attribute == xvGamma2 && (IS_I9XX(pI830))) {
+ } else if (attribute == xvGamma2 && (IS_I9XX(intel))) {
*value = pPriv->gamma2;
- } else if (attribute == xvGamma3 && (IS_I9XX(pI830))) {
+ } else if (attribute == xvGamma3 && (IS_I9XX(intel))) {
*value = pPriv->gamma3;
- } else if (attribute == xvGamma4 && (IS_I9XX(pI830))) {
+ } else if (attribute == xvGamma4 && (IS_I9XX(intel))) {
*value = pPriv->gamma4;
- } else if (attribute == xvGamma5 && (IS_I9XX(pI830))) {
+ } else if (attribute == xvGamma5 && (IS_I9XX(intel))) {
*value = pPriv->gamma5;
} else if (attribute == xvColorKey) {
*value = pPriv->colorKey;
@@ -1254,15 +1254,15 @@ i830_display_overlay(ScrnInfoPtr pScrn, xf86CrtcPtr crtc,
BoxPtr dstBox, short src_w, short src_h, short drw_w,
short drw_h)
{
- I830Ptr pI830 = I830PTR(pScrn);
- I830PortPrivPtr pPriv = pI830->adaptor->pPortPrivates[0].ptr;
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
+ I830PortPrivPtr pPriv = intel->adaptor->pPortPrivates[0].ptr;
int tmp;
OVERLAY_DEBUG("I830DisplayVideo: %dx%d (pitch %d)\n", width, height,
dstPitch);
#if VIDEO_DEBUG
- CompareOverlay(pI830, (uint32_t *) overlay, 0x100);
+ CompareOverlay(intel, (uint32_t *) overlay, 0x100);
#endif
/*
@@ -1372,7 +1372,7 @@ static void
i830_wait_for_scanline(ScrnInfoPtr pScrn, PixmapPtr pPixmap,
xf86CrtcPtr crtc, RegionPtr clipBoxes)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
BoxPtr box;
pixman_box16_t box_in_crtc_coordinates;
int pipe = -1, event, load_scan_lines_pipe;
@@ -1413,7 +1413,7 @@ static Bool
i830_setup_video_buffer(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv,
int alloc_size, int id)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
/* Free the current buffer if we're going to have to reallocate */
if (pPriv->buf && pPriv->buf->size < alloc_size) {
drm_intel_bo_unreference(pPriv->buf);
@@ -1424,7 +1424,7 @@ i830_setup_video_buffer(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv,
i830_free_video_buffers(pPriv);
} else {
if (pPriv->buf == NULL) {
- pPriv->buf = drm_intel_bo_alloc(pI830->bufmgr,
+ pPriv->buf = drm_intel_bo_alloc(intel->bufmgr,
"xv buffer", alloc_size,
4096);
if (pPriv->buf == NULL)
@@ -1440,7 +1440,7 @@ i830_dst_pitch_and_size(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, short width,
short height, int *dstPitch, int *dstPitch2, int *size,
int id)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
int pitchAlignMask;
/* Only needs to be DWORD-aligned for textured on i915, but overlay has
@@ -1450,11 +1450,11 @@ i830_dst_pitch_and_size(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, short width,
pitchAlignMask = 3;
#ifdef INTEL_XVMC
/* for i915 xvmc, hw requires at least 1kb aligned surface */
- if ((id == FOURCC_XVMC) && IS_I915(pI830))
+ if ((id == FOURCC_XVMC) && IS_I915(intel))
pitchAlignMask = 0x3ff;
#endif
} else {
- if (IS_I965G(pI830))
+ if (IS_I965G(intel))
pitchAlignMask = 255;
else
pitchAlignMask = 63;
@@ -1513,7 +1513,7 @@ i830_copy_video_data(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv,
INT32 x1, INT32 y1, INT32 x2, INT32 y2,
int id, unsigned char *buf)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
int srcPitch = 0, srcPitch2 = 0;
int top, left, npixels, nlines, size;
@@ -1532,7 +1532,7 @@ i830_copy_video_data(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv,
/* fixup pointers */
#ifdef INTEL_XVMC
- if (id == FOURCC_XVMC && IS_I915(pI830)) {
+ if (id == FOURCC_XVMC && IS_I915(intel)) {
pPriv->YBufOffset = (uint32_t) ((uintptr_t) buf);
pPriv->VBufOffset = pPriv->YBufOffset + (*dstPitch2 * height);
pPriv->UBufOffset =
@@ -1601,7 +1601,7 @@ I830PutImage(ScrnInfoPtr pScrn,
short width, short height,
Bool sync, RegionPtr clipBoxes, pointer data, DrawablePtr pDraw)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
I830PortPrivPtr pPriv = (I830PortPrivPtr) data;
ScreenPtr pScreen = screenInfo.screens[pScrn->scrnIndex];
PixmapPtr pPixmap = get_drawable_pixmap(pDraw);;
@@ -1678,7 +1678,7 @@ I830PutImage(ScrnInfoPtr pScrn,
i830_wait_for_scanline(pScrn, pPixmap, crtc, clipBoxes);
}
- if (IS_I965G(pI830)) {
+ if (IS_I965G(intel)) {
if (xvmc_passthrough(id, pPriv->rotation)) {
/* XXX: KMS */
pPriv->YBufOffset = (uintptr_t) buf;
@@ -1713,14 +1713,14 @@ I830QueryImageAttributes(ScrnInfoPtr pScrn,
unsigned short *w, unsigned short *h,
int *pitches, int *offsets)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
int size, tmp;
#if 0
ErrorF("I830QueryImageAttributes: w is %d, h is %d\n", *w, *h);
#endif
- if (IS_845G(pI830) || IS_I830(pI830)) {
+ if (IS_845G(intel) || IS_I830(intel)) {
if (*w > IMAGE_MAX_WIDTH_LEGACY)
*w = IMAGE_MAX_WIDTH_LEGACY;
if (*h > IMAGE_MAX_HEIGHT_LEGACY)
@@ -1798,11 +1798,11 @@ I830VideoBlockHandler(int i, pointer blockData, pointer pTimeout,
pointer pReadmask)
{
ScrnInfoPtr pScrn = xf86Screens[i];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
I830PortPrivPtr pPriv;
/* no overlay */
- if (pI830->adaptor == NULL)
+ if (intel->adaptor == NULL)
return;
pPriv = GET_PORT_PRIVATE(pScrn);
diff --git a/src/i830_video.h b/src/i830_video.h
index ac478018..2905be3e 100644
--- a/src/i830_video.h
+++ b/src/i830_video.h
@@ -60,13 +60,13 @@ typedef struct {
int oneLineMode;
int scaleRatio;
Bool textured;
- Rotation rotation; /* should remove I830->rotation later */
+ Rotation rotation; /* should remove intel->rotation later */
int SyncToVblank; /* -1: auto, 0: off, 1: on */
} I830PortPrivRec, *I830PortPrivPtr;
#define GET_PORT_PRIVATE(pScrn) \
- (I830PortPrivPtr)((I830PTR(pScrn))->adaptor->pPortPrivates[0].ptr)
+ (I830PortPrivPtr)((intel_get_screen_private(pScrn))->adaptor->pPortPrivates[0].ptr)
void I915DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv,
int id, RegionPtr dstRegion, short width,
diff --git a/src/i915_3d.c b/src/i915_3d.c
index deee6968..053a94f4 100644
--- a/src/i915_3d.c
+++ b/src/i915_3d.c
@@ -36,7 +36,7 @@
void I915EmitInvarientState(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
BEGIN_BATCH(24);
diff --git a/src/i915_hwmc.c b/src/i915_hwmc.c
index 02e5fe88..1c1acedb 100644
--- a/src/i915_hwmc.c
+++ b/src/i915_hwmc.c
@@ -210,11 +210,11 @@ static void cleanupI915XvMC(I915XvMCPtr xvmc)
static Bool i915_map_xvmc_buffers(ScrnInfoPtr pScrn,
I915XvMCContextPriv * ctxpriv)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
- if (drmAddMap(pI830->drmSubFD,
+ if (drmAddMap(intel->drmSubFD,
(drm_handle_t) (ctxpriv->mcStaticIndirectState->offset +
- pI830->LinearAddr),
+ intel->LinearAddr),
ctxpriv->mcStaticIndirectState->size, DRM_AGP, 0,
(drmAddress) & ctxpriv->sis_handle) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -222,9 +222,9 @@ static Bool i915_map_xvmc_buffers(ScrnInfoPtr pScrn,
return FALSE;
}
- if (drmAddMap(pI830->drmSubFD,
+ if (drmAddMap(intel->drmSubFD,
(drm_handle_t) (ctxpriv->mcSamplerState->offset +
- pI830->LinearAddr),
+ intel->LinearAddr),
ctxpriv->mcSamplerState->size, DRM_AGP, 0,
(drmAddress) & ctxpriv->ssb_handle) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -232,9 +232,9 @@ static Bool i915_map_xvmc_buffers(ScrnInfoPtr pScrn,
return FALSE;
}
- if (drmAddMap(pI830->drmSubFD,
+ if (drmAddMap(intel->drmSubFD,
(drm_handle_t) (ctxpriv->mcMapState->offset +
- pI830->LinearAddr),
+ intel->LinearAddr),
ctxpriv->mcMapState->size, DRM_AGP, 0,
(drmAddress) & ctxpriv->msb_handle) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -242,9 +242,9 @@ static Bool i915_map_xvmc_buffers(ScrnInfoPtr pScrn,
return FALSE;
}
- if (drmAddMap(pI830->drmSubFD,
+ if (drmAddMap(intel->drmSubFD,
(drm_handle_t) (ctxpriv->mcPixelShaderProgram->offset +
- pI830->LinearAddr),
+ intel->LinearAddr),
ctxpriv->mcPixelShaderProgram->size, DRM_AGP, 0,
(drmAddress) & ctxpriv->psp_handle) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -252,9 +252,9 @@ static Bool i915_map_xvmc_buffers(ScrnInfoPtr pScrn,
return FALSE;
}
- if (drmAddMap(pI830->drmSubFD,
+ if (drmAddMap(intel->drmSubFD,
(drm_handle_t) (ctxpriv->mcPixelShaderConstants->offset +
- pI830->LinearAddr),
+ intel->LinearAddr),
ctxpriv->mcPixelShaderConstants->size, DRM_AGP, 0,
(drmAddress) & ctxpriv->psc_handle) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -262,9 +262,9 @@ static Bool i915_map_xvmc_buffers(ScrnInfoPtr pScrn,
return FALSE;
}
- if (drmAddMap(pI830->drmSubFD,
+ if (drmAddMap(intel->drmSubFD,
(drm_handle_t) (ctxpriv->mcCorrdata->offset +
- pI830->LinearAddr),
+ intel->LinearAddr),
ctxpriv->mcCorrdata->size, DRM_AGP, 0,
(drmAddress) & ctxpriv->corrdata_handle) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -278,35 +278,35 @@ static Bool i915_map_xvmc_buffers(ScrnInfoPtr pScrn,
static void i915_unmap_xvmc_buffers(ScrnInfoPtr pScrn,
I915XvMCContextPriv * ctxpriv)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
if (ctxpriv->sis_handle) {
- drmRmMap(pI830->drmSubFD, ctxpriv->sis_handle);
+ drmRmMap(intel->drmSubFD, ctxpriv->sis_handle);
ctxpriv->sis_handle = 0;
}
if (ctxpriv->ssb_handle) {
- drmRmMap(pI830->drmSubFD, ctxpriv->ssb_handle);
+ drmRmMap(intel->drmSubFD, ctxpriv->ssb_handle);
ctxpriv->ssb_handle = 0;
}
if (ctxpriv->msb_handle) {
- drmRmMap(pI830->drmSubFD, ctxpriv->msb_handle);
+ drmRmMap(intel->drmSubFD, ctxpriv->msb_handle);
ctxpriv->msb_handle = 0;
}
if (ctxpriv->psp_handle) {
- drmRmMap(pI830->drmSubFD, ctxpriv->psp_handle);
+ drmRmMap(intel->drmSubFD, ctxpriv->psp_handle);
ctxpriv->psp_handle = 0;
}
if (ctxpriv->psc_handle) {
- drmRmMap(pI830->drmSubFD, ctxpriv->psc_handle);
+ drmRmMap(intel->drmSubFD, ctxpriv->psc_handle);
ctxpriv->psc_handle = 0;
}
if (ctxpriv->corrdata_handle) {
- drmRmMap(pI830->drmSubFD, ctxpriv->corrdata_handle);
+ drmRmMap(intel->drmSubFD, ctxpriv->corrdata_handle);
ctxpriv->corrdata_handle = 0;
}
@@ -315,11 +315,11 @@ static void i915_unmap_xvmc_buffers(ScrnInfoPtr pScrn,
static Bool i915_allocate_xvmc_buffers(ScrnInfoPtr pScrn,
I915XvMCContextPriv * ctxpriv)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
int flags = ALIGN_BOTH_ENDS;
/* on 915G/GM, load indirect can only use physical address...sigh */
- if (IS_I915G(pI830) || IS_I915GM(pI830))
+ if (IS_I915G(intel) || IS_I915GM(intel))
flags |= NEED_PHYSICAL_ADDR;
if (!i830_allocate_xvmc_buffer(pScrn, "[XvMC]Static Indirect State",
@@ -415,7 +415,7 @@ static void i915_free_xvmc_buffers(ScrnInfoPtr pScrn,
static int i915_xvmc_create_context(ScrnInfoPtr pScrn, XvMCContextPtr pContext,
int *num_priv, long **priv)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
I915XvMCCreateContextRec *contextRec = NULL;
I915XvMCPtr pXvMC = (I915XvMCPtr) xvmc_driver->devPrivate;
I915XvMCContextPriv *ctxpriv = NULL;
@@ -424,7 +424,7 @@ static int i915_xvmc_create_context(ScrnInfoPtr pScrn, XvMCContextPtr pContext,
*priv = NULL;
*num_priv = 0;
- if (!pI830->XvMCEnabled) {
+ if (!intel->XvMCEnabled) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[XvMC] i915: XvMC disabled!\n");
return BadAlloc;
@@ -513,11 +513,11 @@ static int i915_xvmc_create_context(ScrnInfoPtr pScrn, XvMCContextPtr pContext,
contextRec->corrdata.handle = ctxpriv->corrdata_handle;
contextRec->corrdata.offset = ctxpriv->mcCorrdata->offset;
contextRec->corrdata.size = ctxpriv->mcCorrdata->size;
- contextRec->deviceID = DEVICE_ID(pI830->PciInfo);
+ contextRec->deviceID = DEVICE_ID(intel->PciInfo);
/* XXX: KMS */
#if 0
- if (IS_I915G(pI830) || IS_I915GM(pI830)) {
+ if (IS_I915G(intel) || IS_I915GM(intel)) {
contextRec->sis.bus_addr =
ctxpriv->mcStaticIndirectState->bus_addr;
contextRec->ssb.bus_addr = ctxpriv->mcSamplerState->bus_addr;
@@ -539,7 +539,7 @@ static int i915_xvmc_create_context(ScrnInfoPtr pScrn, XvMCContextPtr pContext,
static int i915_xvmc_create_surface(ScrnInfoPtr pScrn, XvMCSurfacePtr pSurf,
int *num_priv, long **priv)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
I915XvMCPtr pXvMC = (I915XvMCPtr) xvmc_driver->devPrivate;
I915XvMCSurfacePriv *sfpriv = NULL;
I915XvMCCreateSurfaceRec *surfaceRec = NULL;
@@ -547,7 +547,7 @@ static int i915_xvmc_create_surface(ScrnInfoPtr pScrn, XvMCSurfacePtr pSurf,
unsigned int srfno;
unsigned long bufsize;
- if (!pI830->XvMCEnabled) {
+ if (!intel->XvMCEnabled) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[XvMC] i915: XvMC disabled!\n");
return BadAlloc;
@@ -608,9 +608,9 @@ static int i915_xvmc_create_surface(ScrnInfoPtr pScrn, XvMCSurfacePtr pSurf,
if (0)
i830_describe_allocations(pScrn, 1, "");
- if (drmAddMap(pI830->drmSubFD,
+ if (drmAddMap(intel->drmSubFD,
(drm_handle_t) (sfpriv->surface->offset +
- pI830->LinearAddr), sfpriv->surface->size,
+ intel->LinearAddr), sfpriv->surface->size,
DRM_AGP, 0, (drmAddress) & sfpriv->surface_handle) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[drm] drmAddMap(surface_handle) failed!\n");
@@ -637,7 +637,7 @@ static int i915_xvmc_create_surface(ScrnInfoPtr pScrn, XvMCSurfacePtr pSurf,
static int i915_xvmc_create_subpict(ScrnInfoPtr pScrn, XvMCSubpicturePtr pSubp,
int *num_priv, long **priv)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
I915XvMCPtr pXvMC = (I915XvMCPtr) xvmc_driver->devPrivate;
I915XvMCSurfacePriv *sfpriv = NULL;
I915XvMCCreateSurfaceRec *surfaceRec = NULL;
@@ -697,9 +697,9 @@ static int i915_xvmc_create_subpict(ScrnInfoPtr pScrn, XvMCSubpicturePtr pSubp,
return BadAlloc;
}
- if (drmAddMap(pI830->drmSubFD,
+ if (drmAddMap(intel->drmSubFD,
(drm_handle_t) (sfpriv->surface->offset +
- pI830->LinearAddr), sfpriv->surface->size,
+ intel->LinearAddr), sfpriv->surface->size,
DRM_AGP, 0, (drmAddress) & sfpriv->surface_handle) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[drm] drmAddMap(surface_handle) failed!\n");
@@ -746,13 +746,13 @@ static void i915_xvmc_destroy_context(ScrnInfoPtr pScrn,
static void i915_xvmc_destroy_surface(ScrnInfoPtr pScrn, XvMCSurfacePtr pSurf)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
I915XvMCPtr pXvMC = (I915XvMCPtr) xvmc_driver->devPrivate;
int i;
for (i = 0; i < I915_XVMC_MAX_SURFACES; i++) {
if (pXvMC->surfaces[i] == pSurf->surface_id) {
- drmRmMap(pI830->drmSubFD,
+ drmRmMap(intel->drmSubFD,
pXvMC->sfprivs[i]->surface_handle);
i830_free_xvmc_buffer(pScrn,
pXvMC->sfprivs[i]->surface);
@@ -770,13 +770,13 @@ static void i915_xvmc_destroy_surface(ScrnInfoPtr pScrn, XvMCSurfacePtr pSurf)
static void i915_xvmc_destroy_subpict(ScrnInfoPtr pScrn,
XvMCSubpicturePtr pSubp)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
I915XvMCPtr pXvMC = (I915XvMCPtr) xvmc_driver->devPrivate;
int i;
for (i = 0; i < I915_XVMC_MAX_SURFACES; i++) {
if (pXvMC->surfaces[i] == pSubp->subpicture_id) {
- drmRmMap(pI830->drmSubFD,
+ drmRmMap(intel->drmSubFD,
pXvMC->sfprivs[i]->surface_handle);
i830_free_xvmc_buffer(pScrn,
pXvMC->sfprivs[i]->surface);
diff --git a/src/i915_render.c b/src/i915_render.c
index 5a578ab0..389fa9d0 100644
--- a/src/i915_render.c
+++ b/src/i915_render.c
@@ -240,7 +240,7 @@ i915_check_composite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
static Bool i915_texture_setup(PicturePtr pPict, PixmapPtr pPix, int unit)
{
ScrnInfoPtr pScrn = xf86Screens[pPict->pDrawable->pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
uint32_t format, pitch, filter;
int w, h, i;
uint32_t wrap_mode;
@@ -248,8 +248,8 @@ static Bool i915_texture_setup(PicturePtr pPict, PixmapPtr pPix, int unit)
pitch = intel_get_pixmap_pitch(pPix);
w = pPict->pDrawable->width;
h = pPict->pDrawable->height;
- pI830->scale_units[unit][0] = pPix->drawable.width;
- pI830->scale_units[unit][1] = pPix->drawable.height;
+ intel->scale_units[unit][0] = pPix->drawable.width;
+ intel->scale_units[unit][1] = pPix->drawable.height;
for (i = 0; i < sizeof(i915_tex_formats) / sizeof(i915_tex_formats[0]);
i++) {
@@ -292,25 +292,25 @@ static Bool i915_texture_setup(PicturePtr pPict, PixmapPtr pPix, int unit)
}
/* offset filled in at emit time */
- pI830->mapstate[unit * 3 + 0] = 0;
- pI830->mapstate[unit * 3 + 1] = format |
+ intel->mapstate[unit * 3 + 0] = 0;
+ intel->mapstate[unit * 3 + 1] = format |
MS3_USE_FENCE_REGS |
((pPix->drawable.height - 1) << MS3_HEIGHT_SHIFT) |
((pPix->drawable.width - 1) << MS3_WIDTH_SHIFT);
- pI830->mapstate[unit * 3 + 2] = ((pitch / 4) - 1) << MS4_PITCH_SHIFT;
+ intel->mapstate[unit * 3 + 2] = ((pitch / 4) - 1) << MS4_PITCH_SHIFT;
- pI830->samplerstate[unit * 3 + 0] = (MIPFILTER_NONE <<
+ intel->samplerstate[unit * 3 + 0] = (MIPFILTER_NONE <<
SS2_MIP_FILTER_SHIFT);
- pI830->samplerstate[unit * 3 + 0] |= filter;
- pI830->samplerstate[unit * 3 + 1] = SS3_NORMALIZED_COORDS;
- pI830->samplerstate[unit * 3 + 1] |=
+ intel->samplerstate[unit * 3 + 0] |= filter;
+ intel->samplerstate[unit * 3 + 1] = SS3_NORMALIZED_COORDS;
+ intel->samplerstate[unit * 3 + 1] |=
wrap_mode << SS3_TCX_ADDR_MODE_SHIFT;
- pI830->samplerstate[unit * 3 + 1] |=
+ intel->samplerstate[unit * 3 + 1] |=
wrap_mode << SS3_TCY_ADDR_MODE_SHIFT;
- pI830->samplerstate[unit * 3 + 1] |= unit << SS3_TEXTUREMAP_INDEX_SHIFT;
- pI830->samplerstate[unit * 3 + 2] = 0x00000000; /* border color */
+ intel->samplerstate[unit * 3 + 1] |= unit << SS3_TEXTUREMAP_INDEX_SHIFT;
+ intel->samplerstate[unit * 3 + 2] = 0x00000000; /* border color */
- pI830->transform[unit] = pPict->transform;
+ intel->transform[unit] = pPict->transform;
return TRUE;
}
@@ -321,7 +321,7 @@ i915_prepare_composite(int op, PicturePtr pSrcPicture,
PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst)
{
ScrnInfoPtr pScrn = xf86Screens[pSrcPicture->pDrawable->pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
drm_intel_bo *bo_table[] = {
NULL, /* batch_bo */
i830_get_pixmap_bo(pSrc),
@@ -329,12 +329,12 @@ i915_prepare_composite(int op, PicturePtr pSrcPicture,
i830_get_pixmap_bo(pDst),
};
- pI830->render_src_picture = pSrcPicture;
- pI830->render_src = pSrc;
- pI830->render_mask_picture = pMaskPicture;
- pI830->render_mask = pMask;
- pI830->render_dst_picture = pDstPicture;
- pI830->render_dst = pDst;
+ intel->render_src_picture = pSrcPicture;
+ intel->render_src = pSrc;
+ intel->render_mask_picture = pMaskPicture;
+ intel->render_mask = pMask;
+ intel->render_dst_picture = pDstPicture;
+ intel->render_dst = pDst;
i830_exa_check_pitch_3d(pSrc);
if (pMask)
@@ -342,7 +342,7 @@ i915_prepare_composite(int op, PicturePtr pSrcPicture,
i830_exa_check_pitch_3d(pDst);
if (!i915_get_dest_format(pDstPicture,
- &pI830->i915_render_state.dst_format))
+ &intel->i915_render_state.dst_format))
return FALSE;
if (!i830_get_aperture_space(pScrn, bo_table, ARRAY_SIZE(bo_table)))
@@ -351,88 +351,88 @@ i915_prepare_composite(int op, PicturePtr pSrcPicture,
if (!i915_texture_setup(pSrcPicture, pSrc, 0))
I830FALLBACK("fail to setup src texture\n");
- pI830->dst_coord_adjust = 0;
- pI830->src_coord_adjust = 0;
- pI830->mask_coord_adjust = 0;
+ intel->dst_coord_adjust = 0;
+ intel->src_coord_adjust = 0;
+ intel->mask_coord_adjust = 0;
if (pSrcPicture->filter == PictFilterNearest)
- pI830->dst_coord_adjust = -0.125;
+ intel->dst_coord_adjust = -0.125;
if (pMask != NULL) {
if (!i915_texture_setup(pMaskPicture, pMask, 1))
I830FALLBACK("fail to setup mask texture\n");
if (pMaskPicture->filter == PictFilterNearest)
- pI830->dst_coord_adjust = -0.125;
+ intel->dst_coord_adjust = -0.125;
} else {
- pI830->transform[1] = NULL;
- pI830->scale_units[1][0] = -1;
- pI830->scale_units[1][1] = -1;
+ intel->transform[1] = NULL;
+ intel->scale_units[1][0] = -1;
+ intel->scale_units[1][1] = -1;
}
- pI830->i915_render_state.op = op;
- pI830->i915_render_state.needs_emit = TRUE;
+ intel->i915_render_state.op = op;
+ intel->i915_render_state.needs_emit = TRUE;
return TRUE;
}
static void i915_emit_composite_setup(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
- int op = pI830->i915_render_state.op;
- PicturePtr pSrcPicture = pI830->render_src_picture;
- PicturePtr pMaskPicture = pI830->render_mask_picture;
- PicturePtr pDstPicture = pI830->render_dst_picture;
- PixmapPtr pSrc = pI830->render_src;
- PixmapPtr pMask = pI830->render_mask;
- PixmapPtr pDst = pI830->render_dst;
- uint32_t dst_format = pI830->i915_render_state.dst_format, dst_pitch;
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
+ int op = intel->i915_render_state.op;
+ PicturePtr pSrcPicture = intel->render_src_picture;
+ PicturePtr pMaskPicture = intel->render_mask_picture;
+ PicturePtr pDstPicture = intel->render_dst_picture;
+ PixmapPtr pSrc = intel->render_src;
+ PixmapPtr pMask = intel->render_mask;
+ PixmapPtr pDst = intel->render_dst;
+ uint32_t dst_format = intel->i915_render_state.dst_format, dst_pitch;
uint32_t blendctl;
int out_reg = FS_OC;
FS_LOCALS(20);
Bool is_affine_src, is_affine_mask;
- pI830->i915_render_state.needs_emit = FALSE;
+ intel->i915_render_state.needs_emit = FALSE;
IntelEmitInvarientState(pScrn);
- pI830->last_3d = LAST_3D_RENDER;
+ intel->last_3d = LAST_3D_RENDER;
dst_pitch = intel_get_pixmap_pitch(pDst);
- is_affine_src = i830_transform_is_affine(pI830->transform[0]);
- is_affine_mask = i830_transform_is_affine(pI830->transform[1]);
+ is_affine_src = i830_transform_is_affine(intel->transform[0]);
+ is_affine_mask = i830_transform_is_affine(intel->transform[1]);
if (pMask == NULL) {
BEGIN_BATCH(10);
OUT_BATCH(_3DSTATE_MAP_STATE | 3);
OUT_BATCH(0x00000001); /* map 0 */
OUT_RELOC_PIXMAP(pSrc, I915_GEM_DOMAIN_SAMPLER, 0, 0);
- OUT_BATCH(pI830->mapstate[1]);
- OUT_BATCH(pI830->mapstate[2]);
+ OUT_BATCH(intel->mapstate[1]);
+ OUT_BATCH(intel->mapstate[2]);
OUT_BATCH(_3DSTATE_SAMPLER_STATE | 3);
OUT_BATCH(0x00000001); /* sampler 0 */
- OUT_BATCH(pI830->samplerstate[0]);
- OUT_BATCH(pI830->samplerstate[1]);
- OUT_BATCH(pI830->samplerstate[2]);
+ OUT_BATCH(intel->samplerstate[0]);
+ OUT_BATCH(intel->samplerstate[1]);
+ OUT_BATCH(intel->samplerstate[2]);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(16);
OUT_BATCH(_3DSTATE_MAP_STATE | 6);
OUT_BATCH(0x00000003); /* map 0,1 */
OUT_RELOC_PIXMAP(pSrc, I915_GEM_DOMAIN_SAMPLER, 0, 0);
- OUT_BATCH(pI830->mapstate[1]);
- OUT_BATCH(pI830->mapstate[2]);
+ OUT_BATCH(intel->mapstate[1]);
+ OUT_BATCH(intel->mapstate[2]);
OUT_RELOC_PIXMAP(pMask, I915_GEM_DOMAIN_SAMPLER, 0, 0);
- OUT_BATCH(pI830->mapstate[4]);
- OUT_BATCH(pI830->mapstate[5]);
+ OUT_BATCH(intel->mapstate[4]);
+ OUT_BATCH(intel->mapstate[5]);
OUT_BATCH(_3DSTATE_SAMPLER_STATE | 6);
OUT_BATCH(0x00000003); /* sampler 0,1 */
- OUT_BATCH(pI830->samplerstate[0]);
- OUT_BATCH(pI830->samplerstate[1]);
- OUT_BATCH(pI830->samplerstate[2]);
- OUT_BATCH(pI830->samplerstate[3]);
- OUT_BATCH(pI830->samplerstate[4]);
- OUT_BATCH(pI830->samplerstate[5]);
+ OUT_BATCH(intel->samplerstate[0]);
+ OUT_BATCH(intel->samplerstate[1]);
+ OUT_BATCH(intel->samplerstate[2]);
+ OUT_BATCH(intel->samplerstate[3]);
+ OUT_BATCH(intel->samplerstate[4]);
+ OUT_BATCH(intel->samplerstate[5]);
ADVANCE_BATCH();
}
{
@@ -571,7 +571,7 @@ i915_emit_composite_primitive(PixmapPtr pDst,
int dstX, int dstY, int w, int h)
{
ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
Bool is_affine_src, is_affine_mask = TRUE;
int per_vertex, num_floats;
float src_x[3], src_y[3], src_w[3], mask_x[3], mask_y[3], mask_w[3];
@@ -579,27 +579,27 @@ i915_emit_composite_primitive(PixmapPtr pDst,
per_vertex = 2; /* dest x/y */
{
- float x = srcX + pI830->src_coord_adjust;
- float y = srcY + pI830->src_coord_adjust;
+ float x = srcX + intel->src_coord_adjust;
+ float y = srcY + intel->src_coord_adjust;
- is_affine_src = i830_transform_is_affine(pI830->transform[0]);
+ is_affine_src = i830_transform_is_affine(intel->transform[0]);
if (is_affine_src) {
if (!i830_get_transformed_coordinates(x, y,
- pI830->
+ intel->
transform[0],
&src_x[0],
&src_y[0]))
return;
if (!i830_get_transformed_coordinates(x, y + h,
- pI830->
+ intel->
transform[0],
&src_x[1],
&src_y[1]))
return;
if (!i830_get_transformed_coordinates(x + w, y + h,
- pI830->
+ intel->
transform[0],
&src_x[2],
&src_y[2]))
@@ -608,7 +608,7 @@ i915_emit_composite_primitive(PixmapPtr pDst,
per_vertex += 2; /* src x/y */
} else {
if (!i830_get_transformed_coordinates_3d(x, y,
- pI830->
+ intel->
transform[0],
&src_x[0],
&src_y[0],
@@ -616,7 +616,7 @@ i915_emit_composite_primitive(PixmapPtr pDst,
return;
if (!i830_get_transformed_coordinates_3d(x, y + h,
- pI830->
+ intel->
transform[0],
&src_x[1],
&src_y[1],
@@ -624,7 +624,7 @@ i915_emit_composite_primitive(PixmapPtr pDst,
return;
if (!i830_get_transformed_coordinates_3d(x + w, y + h,
- pI830->
+ intel->
transform[0],
&src_x[2],
&src_y[2],
@@ -635,28 +635,28 @@ i915_emit_composite_primitive(PixmapPtr pDst,
}
}
- if (pI830->render_mask) {
- float x = maskX + pI830->mask_coord_adjust;
- float y = maskY + pI830->mask_coord_adjust;
+ if (intel->render_mask) {
+ float x = maskX + intel->mask_coord_adjust;
+ float y = maskY + intel->mask_coord_adjust;
- is_affine_mask = i830_transform_is_affine(pI830->transform[1]);
+ is_affine_mask = i830_transform_is_affine(intel->transform[1]);
if (is_affine_mask) {
if (!i830_get_transformed_coordinates(x, y,
- pI830->
+ intel->
transform[1],
&mask_x[0],
&mask_y[0]))
return;
if (!i830_get_transformed_coordinates(x, y + h,
- pI830->
+ intel->
transform[1],
&mask_x[1],
&mask_y[1]))
return;
if (!i830_get_transformed_coordinates(x + w, y + h,
- pI830->
+ intel->
transform[1],
&mask_x[2],
&mask_y[2]))
@@ -665,7 +665,7 @@ i915_emit_composite_primitive(PixmapPtr pDst,
per_vertex += 2; /* mask x/y */
} else {
if (!i830_get_transformed_coordinates_3d(x, y,
- pI830->
+ intel->
transform[1],
&mask_x[0],
&mask_y[0],
@@ -673,7 +673,7 @@ i915_emit_composite_primitive(PixmapPtr pDst,
return;
if (!i830_get_transformed_coordinates_3d(x, y + h,
- pI830->
+ intel->
transform[1],
&mask_x[1],
&mask_y[1],
@@ -681,7 +681,7 @@ i915_emit_composite_primitive(PixmapPtr pDst,
return;
if (!i830_get_transformed_coordinates_3d(x + w, y + h,
- pI830->
+ intel->
transform[1],
&mask_x[2],
&mask_y[2],
@@ -697,51 +697,51 @@ i915_emit_composite_primitive(PixmapPtr pDst,
BEGIN_BATCH(1 + num_floats);
OUT_BATCH(PRIM3D_INLINE | PRIM3D_RECTLIST | (num_floats - 1));
- OUT_BATCH_F(pI830->dst_coord_adjust + dstX + w);
- OUT_BATCH_F(pI830->dst_coord_adjust + dstY + h);
- OUT_BATCH_F(src_x[2] / pI830->scale_units[0][0]);
- OUT_BATCH_F(src_y[2] / pI830->scale_units[0][1]);
+ OUT_BATCH_F(intel->dst_coord_adjust + dstX + w);
+ OUT_BATCH_F(intel->dst_coord_adjust + dstY + h);
+ OUT_BATCH_F(src_x[2] / intel->scale_units[0][0]);
+ OUT_BATCH_F(src_y[2] / intel->scale_units[0][1]);
if (!is_affine_src) {
OUT_BATCH_F(0.0);
OUT_BATCH_F(src_w[2]);
}
- if (pI830->render_mask) {
- OUT_BATCH_F(mask_x[2] / pI830->scale_units[1][0]);
- OUT_BATCH_F(mask_y[2] / pI830->scale_units[1][1]);
+ if (intel->render_mask) {
+ OUT_BATCH_F(mask_x[2] / intel->scale_units[1][0]);
+ OUT_BATCH_F(mask_y[2] / intel->scale_units[1][1]);
if (!is_affine_mask) {
OUT_BATCH_F(0.0);
OUT_BATCH_F(mask_w[2]);
}
}
- OUT_BATCH_F(pI830->dst_coord_adjust + dstX);
- OUT_BATCH_F(pI830->dst_coord_adjust + dstY + h);
- OUT_BATCH_F(src_x[1] / pI830->scale_units[0][0]);
- OUT_BATCH_F(src_y[1] / pI830->scale_units[0][1]);
+ OUT_BATCH_F(intel->dst_coord_adjust + dstX);
+ OUT_BATCH_F(intel->dst_coord_adjust + dstY + h);
+ OUT_BATCH_F(src_x[1] / intel->scale_units[0][0]);
+ OUT_BATCH_F(src_y[1] / intel->scale_units[0][1]);
if (!is_affine_src) {
OUT_BATCH_F(0.0);
OUT_BATCH_F(src_w[1]);
}
- if (pI830->render_mask) {
- OUT_BATCH_F(mask_x[1] / pI830->scale_units[1][0]);
- OUT_BATCH_F(mask_y[1] / pI830->scale_units[1][1]);
+ if (intel->render_mask) {
+ OUT_BATCH_F(mask_x[1] / intel->scale_units[1][0]);
+ OUT_BATCH_F(mask_y[1] / intel->scale_units[1][1]);
if (!is_affine_mask) {
OUT_BATCH_F(0.0);
OUT_BATCH_F(mask_w[1]);
}
}
- OUT_BATCH_F(pI830->dst_coord_adjust + dstX);
- OUT_BATCH_F(pI830->dst_coord_adjust + dstY);
- OUT_BATCH_F(src_x[0] / pI830->scale_units[0][0]);
- OUT_BATCH_F(src_y[0] / pI830->scale_units[0][1]);
+ OUT_BATCH_F(intel->dst_coord_adjust + dstX);
+ OUT_BATCH_F(intel->dst_coord_adjust + dstY);
+ OUT_BATCH_F(src_x[0] / intel->scale_units[0][0]);
+ OUT_BATCH_F(src_y[0] / intel->scale_units[0][1]);
if (!is_affine_src) {
OUT_BATCH_F(0.0);
OUT_BATCH_F(src_w[0]);
}
- if (pI830->render_mask) {
- OUT_BATCH_F(mask_x[0] / pI830->scale_units[1][0]);
- OUT_BATCH_F(mask_y[0] / pI830->scale_units[1][1]);
+ if (intel->render_mask) {
+ OUT_BATCH_F(mask_x[0] / intel->scale_units[1][0]);
+ OUT_BATCH_F(mask_y[0] / intel->scale_units[1][1]);
if (!is_affine_mask) {
OUT_BATCH_F(0.0);
OUT_BATCH_F(mask_w[0]);
@@ -756,11 +756,11 @@ i915_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
int dstX, int dstY, int w, int h)
{
ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
intel_batch_start_atomic(pScrn, 150);
- if (pI830->i915_render_state.needs_emit)
+ if (intel->i915_render_state.needs_emit)
i915_emit_composite_setup(pScrn);
i915_emit_composite_primitive(pDst, srcX, srcY, maskX, maskY, dstX,
@@ -771,7 +771,7 @@ i915_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
void i915_batch_flush_notify(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
- pI830->i915_render_state.needs_emit = TRUE;
+ intel->i915_render_state.needs_emit = TRUE;
}
diff --git a/src/i915_video.c b/src/i915_video.c
index 59118319..e2080e77 100644
--- a/src/i915_video.c
+++ b/src/i915_video.c
@@ -47,7 +47,7 @@ I915DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
short src_w, short src_h, short drw_w, short drw_h,
PixmapPtr pPixmap)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
uint32_t format, ms3, s5;
BoxPtr pbox = REGION_RECTS(dstRegion);
int nbox_total = REGION_NUM_RECTS(dstRegion);
@@ -65,14 +65,14 @@ I915DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
while (nbox_total) {
nbox_this_time = nbox_total;
- if (BYTES_FOR_BOXES(nbox_this_time) > BATCH_BYTES(pI830))
- nbox_this_time = BOXES_IN_BYTES(BATCH_BYTES(pI830));
+ if (BYTES_FOR_BOXES(nbox_this_time) > BATCH_BYTES(intel))
+ nbox_this_time = BOXES_IN_BYTES(BATCH_BYTES(intel));
nbox_total -= nbox_this_time;
intel_batch_start_atomic(pScrn, 200 + 20 * nbox_this_time);
IntelEmitInvarientState(pScrn);
- pI830->last_3d = LAST_3D_VIDEO;
+ intel->last_3d = LAST_3D_VIDEO;
BEGIN_BATCH(20);
@@ -105,7 +105,7 @@ I915DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
OUT_BATCH((1 << S4_POINT_WIDTH_SHIFT) | S4_LINE_WIDTH_ONE |
S4_CULLMODE_NONE | S4_VFMT_XY);
s5 = 0x0;
- if (pI830->cpp == 2)
+ if (intel->cpp == 2)
s5 |= S5_COLOR_DITHER_ENABLE;
OUT_BATCH(s5); /* S5 - enable bits */
OUT_BATCH((2 << S6_DEPTH_TEST_FUNC_SHIFT) |
@@ -117,7 +117,7 @@ I915DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
OUT_BATCH(0x00000000);
OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
- if (pI830->cpp == 2)
+ if (intel->cpp == 2)
format = COLR_BUF_RGB565;
else
format =
diff --git a/src/i965_hwmc.c b/src/i965_hwmc.c
index 3c10f4e8..261a2700 100644
--- a/src/i965_hwmc.c
+++ b/src/i965_hwmc.c
@@ -55,7 +55,7 @@ static int create_context(ScrnInfoPtr pScrn,
CARD32 ** private)
{
struct i965_xvmc_context *private_context, *context_dup;
- I830Ptr I830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
unsigned int blocknum =
(((context->width + 15) / 16) * ((context->height + 15) / 16));
@@ -71,9 +71,9 @@ static int create_context(ScrnInfoPtr pScrn,
return BadAlloc;
}
- private_context->is_g4x = IS_G4X(I830);
- private_context->is_965_q = IS_965_Q(I830);
- private_context->is_igdng = IS_IGDNG(I830);
+ private_context->is_g4x = IS_G4X(intel);
+ private_context->is_965_q = IS_965_Q(intel);
+ private_context->is_igdng = IS_IGDNG(intel);
private_context->comm.kernel_exec_fencing = 1;
private_context->comm.type = xvmc_driver->flag;
@@ -158,17 +158,17 @@ static int put_image(ScrnInfoPtr pScrn,
short height, Bool sync, RegionPtr clipBoxes, pointer data,
DrawablePtr pDraw)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
struct intel_xvmc_command *cmd = (struct intel_xvmc_command *)buf;
dri_bo *bo;
if (id == FOURCC_XVMC) {
- bo = intel_bo_gem_create_from_name(pI830->bufmgr, "surface",
+ bo = intel_bo_gem_create_from_name(intel->bufmgr, "surface",
cmd->handle);
dri_bo_pin(bo, 0x1000);
/* XXX: KMS */
#if 0
- buf = pI830->FbBase + bo->offset;
+ buf = intel->FbBase + bo->offset;
#endif
}
XvPutImage(pScrn, src_x, src_y, drw_x, drw_y, src_w, src_h,
diff --git a/src/i965_render.c b/src/i965_render.c
index 8fa3c0f1..9f4b1c0b 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -630,11 +630,11 @@ struct gen4_render_state {
static drm_intel_bo *gen4_create_sf_state(ScrnInfoPtr scrn,
drm_intel_bo * kernel_bo)
{
- I830Ptr pI830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
struct brw_sf_unit_state *sf_state;
drm_intel_bo *sf_state_bo;
- sf_state_bo = drm_intel_bo_alloc(pI830->bufmgr, "gen4 SF state",
+ sf_state_bo = drm_intel_bo_alloc(intel->bufmgr, "gen4 SF state",
sizeof(*sf_state), 4096);
drm_intel_bo_map(sf_state_bo, TRUE);
sf_state = sf_state_bo->virtual;
@@ -772,12 +772,12 @@ static drm_intel_bo *gen4_create_sampler_state(ScrnInfoPtr scrn,
mask_extend,
drm_intel_bo * border_color_bo)
{
- I830Ptr pI830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
drm_intel_bo *sampler_state_bo;
struct brw_sampler_state *sampler_state;
sampler_state_bo =
- drm_intel_bo_alloc(pI830->bufmgr, "gen4 sampler state",
+ drm_intel_bo_alloc(intel->bufmgr, "gen4 sampler state",
sizeof(struct brw_sampler_state) * 2, 4096);
drm_intel_bo_map(sampler_state_bo, TRUE);
sampler_state = sampler_state_bo->virtual;
@@ -840,11 +840,11 @@ static drm_intel_bo *gen4_create_wm_state(ScrnInfoPtr scrn,
drm_intel_bo * kernel_bo,
drm_intel_bo * sampler_bo)
{
- I830Ptr pI830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
struct brw_wm_unit_state *wm_state;
drm_intel_bo *wm_state_bo;
- wm_state_bo = drm_intel_bo_alloc(pI830->bufmgr, "gen4 WM state",
+ wm_state_bo = drm_intel_bo_alloc(intel->bufmgr, "gen4 WM state",
sizeof(*wm_state), 4096);
drm_intel_bo_map(wm_state_bo, TRUE);
wm_state = wm_state_bo->virtual;
@@ -872,7 +872,7 @@ static drm_intel_bo *gen4_create_wm_state(ScrnInfoPtr scrn,
wm_state->wm4.stats_enable = 1; /* statistic */
- if (IS_IGDNG(pI830))
+ if (IS_IGDNG(intel))
wm_state->wm4.sampler_count = 0; /* hardware requirement */
else
wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
@@ -906,7 +906,7 @@ static drm_intel_bo *gen4_create_wm_state(ScrnInfoPtr scrn,
/* binding table entry count is only used for prefetching, and it has to
* be set 0 for IGDNG
*/
- if (IS_IGDNG(pI830))
+ if (IS_IGDNG(intel))
wm_state->thread1.binding_table_entry_count = 0;
drm_intel_bo_unmap(wm_state_bo);
@@ -916,14 +916,14 @@ static drm_intel_bo *gen4_create_wm_state(ScrnInfoPtr scrn,
static drm_intel_bo *gen4_create_cc_viewport(ScrnInfoPtr scrn)
{
- I830Ptr pI830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
drm_intel_bo *bo;
struct brw_cc_viewport cc_viewport;
cc_viewport.min_depth = -1.e35;
cc_viewport.max_depth = 1.e35;
- bo = drm_intel_bo_alloc(pI830->bufmgr, "gen4 render unit state",
+ bo = drm_intel_bo_alloc(intel->bufmgr, "gen4 render unit state",
sizeof(cc_viewport), 4096);
drm_intel_bo_subdata(bo, 0, sizeof(cc_viewport), &cc_viewport);
@@ -932,12 +932,12 @@ static drm_intel_bo *gen4_create_cc_viewport(ScrnInfoPtr scrn)
static drm_intel_bo *gen4_create_vs_unit_state(ScrnInfoPtr scrn)
{
- I830Ptr pI830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
struct brw_vs_unit_state vs_state;
memset(&vs_state, 0, sizeof(vs_state));
/* Set up the vertex shader to be disabled (passthrough) */
- if (IS_IGDNG(pI830))
+ if (IS_IGDNG(intel))
vs_state.thread4.nr_urb_entries = URB_VS_ENTRIES >> 2; /* hardware requirement */
else
vs_state.thread4.nr_urb_entries = URB_VS_ENTRIES;
@@ -955,14 +955,14 @@ static drm_intel_bo *gen4_create_vs_unit_state(ScrnInfoPtr scrn)
*/
static drm_intel_bo *gen4_create_cc_unit_state(ScrnInfoPtr scrn)
{
- I830Ptr pI830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
struct gen4_cc_unit_state *cc_state;
drm_intel_bo *cc_state_bo, *cc_vp_bo;
int i, j;
cc_vp_bo = gen4_create_cc_viewport(scrn);
- cc_state_bo = drm_intel_bo_alloc(pI830->bufmgr, "gen4 CC state",
+ cc_state_bo = drm_intel_bo_alloc(intel->bufmgr, "gen4 CC state",
sizeof(*cc_state), 4096);
drm_intel_bo_map(cc_state_bo, TRUE);
cc_state = cc_state_bo->virtual;
@@ -1096,8 +1096,8 @@ i965_set_picture_surface_state(dri_bo * ss_bo, int ss_index,
static void i965_emit_composite_state(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
- struct gen4_render_state *render_state = pI830->gen4_render_state;
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
+ struct gen4_render_state *render_state = intel->gen4_render_state;
gen4_composite_op *composite_op = &render_state->composite_op;
int op = composite_op->op;
PicturePtr pMaskPicture = composite_op->mask_picture;
@@ -1120,7 +1120,7 @@ static void i965_emit_composite_state(ScrnInfoPtr pScrn)
render_state->needs_state_emit = FALSE;
IntelEmitInvarientState(pScrn);
- pI830->last_3d = LAST_3D_RENDER;
+ intel->last_3d = LAST_3D_RENDER;
urb_vs_start = 0;
urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE;
@@ -1148,13 +1148,13 @@ static void i965_emit_composite_state(ScrnInfoPtr pScrn)
ADVANCE_BATCH();
}
{
- if (IS_IGDNG(pI830))
+ if (IS_IGDNG(intel))
BEGIN_BATCH(14);
else
BEGIN_BATCH(12);
/* Match Mesa driver setup */
- if (IS_G4X(pI830) || IS_IGDNG(pI830))
+ if (IS_G4X(intel) || IS_IGDNG(intel))
OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
else
OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
@@ -1166,7 +1166,7 @@ static void i965_emit_composite_state(ScrnInfoPtr pScrn)
/* Zero out the two base address registers so all offsets are
* absolute.
*/
- if (IS_IGDNG(pI830)) {
+ if (IS_IGDNG(intel)) {
OUT_BATCH(BRW_STATE_BASE_ADDRESS | 6);
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */
@@ -1200,7 +1200,7 @@ static void i965_emit_composite_state(ScrnInfoPtr pScrn)
BEGIN_BATCH(26);
/* Pipe control */
- if (IS_IGDNG(pI830))
+ if (IS_IGDNG(intel))
pipe_ctrl = BRW_PIPE_CONTROL_NOWRITE;
else
pipe_ctrl =
@@ -1309,7 +1309,7 @@ static void i965_emit_composite_state(ScrnInfoPtr pScrn)
w_component = BRW_VFCOMPONENT_STORE_SRC;
}
- if (IS_IGDNG(pI830)) {
+ if (IS_IGDNG(intel)) {
BEGIN_BATCH(pMask ? 9 : 7);
/*
* The reason to add this extra vertex element in the header is that
@@ -1354,7 +1354,7 @@ static void i965_emit_composite_state(ScrnInfoPtr pScrn)
(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
(0 << VE0_OFFSET_SHIFT));
- if (IS_IGDNG(pI830))
+ if (IS_IGDNG(intel))
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC <<
VE1_VFCOMPONENT_0_SHIFT) |
(BRW_VFCOMPONENT_STORE_SRC <<
@@ -1376,7 +1376,7 @@ static void i965_emit_composite_state(ScrnInfoPtr pScrn)
/* u0, v0, w0 */
OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | (src_format << VE0_FORMAT_SHIFT) | ((2 * 4) << VE0_OFFSET_SHIFT)); /* offset vb in bytes */
- if (IS_IGDNG(pI830))
+ if (IS_IGDNG(intel))
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC <<
VE1_VFCOMPONENT_0_SHIFT) |
(BRW_VFCOMPONENT_STORE_SRC <<
@@ -1390,7 +1390,7 @@ static void i965_emit_composite_state(ScrnInfoPtr pScrn)
if (pMask) {
OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | (src_format << VE0_FORMAT_SHIFT) | (((2 + selem) * 4) << VE0_OFFSET_SHIFT)); /* vb offset in bytes */
- if (IS_IGDNG(pI830))
+ if (IS_IGDNG(intel))
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC <<
VE1_VFCOMPONENT_0_SHIFT) |
(BRW_VFCOMPONENT_STORE_SRC <<
@@ -1413,11 +1413,11 @@ static void i965_emit_composite_state(ScrnInfoPtr pScrn)
*/
static Bool i965_composite_check_aperture(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
- struct gen4_render_state *render_state = pI830->gen4_render_state;
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
+ struct gen4_render_state *render_state = intel->gen4_render_state;
gen4_composite_op *composite_op = &render_state->composite_op;
drm_intel_bo *bo_table[] = {
- pI830->batch_bo,
+ intel->batch_bo,
composite_op->binding_table_bo,
render_state->vertex_buffer_bo,
render_state->vs_state_bo,
@@ -1442,8 +1442,8 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst)
{
ScrnInfoPtr pScrn = xf86Screens[pDstPicture->pDrawable->pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
- struct gen4_render_state *render_state = pI830->gen4_render_state;
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
+ struct gen4_render_state *render_state = intel->gen4_render_state;
gen4_composite_op *composite_op = &render_state->composite_op;
uint32_t *binding_table;
drm_intel_bo *binding_table_bo, *surface_state_bo;
@@ -1472,7 +1472,7 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
}
/* Set up the surface states. */
- surface_state_bo = dri_bo_alloc(pI830->bufmgr, "surface_state",
+ surface_state_bo = dri_bo_alloc(intel->bufmgr, "surface_state",
3 * sizeof(brw_surface_state_padded),
4096);
if (dri_bo_map(surface_state_bo, 1) != 0) {
@@ -1493,7 +1493,7 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
dri_bo_unmap(surface_state_bo);
/* Set up the binding table of surface indices to surface state. */
- binding_table_bo = dri_bo_alloc(pI830->bufmgr, "binding_table",
+ binding_table_bo = dri_bo_alloc(intel->bufmgr, "binding_table",
3 * sizeof(uint32_t), 4096);
if (dri_bo_map(binding_table_bo, 1) != 0) {
dri_bo_unreference(binding_table_bo);
@@ -1544,22 +1544,22 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
composite_op->src_filter =
sampler_state_filter_from_picture(pSrcPicture->filter);
- pI830->scale_units[0][0] = pSrc->drawable.width;
- pI830->scale_units[0][1] = pSrc->drawable.height;
+ intel->scale_units[0][0] = pSrc->drawable.width;
+ intel->scale_units[0][1] = pSrc->drawable.height;
- pI830->transform[0] = pSrcPicture->transform;
- composite_op->is_affine = i830_transform_is_affine(pI830->transform[0]);
+ intel->transform[0] = pSrcPicture->transform;
+ composite_op->is_affine = i830_transform_is_affine(intel->transform[0]);
if (!pMask) {
- pI830->transform[1] = NULL;
- pI830->scale_units[1][0] = -1;
- pI830->scale_units[1][1] = -1;
+ intel->transform[1] = NULL;
+ intel->scale_units[1][0] = -1;
+ intel->scale_units[1][1] = -1;
} else {
- pI830->transform[1] = pMaskPicture->transform;
- pI830->scale_units[1][0] = pMask->drawable.width;
- pI830->scale_units[1][1] = pMask->drawable.height;
+ intel->transform[1] = pMaskPicture->transform;
+ intel->scale_units[1][0] = pMask->drawable.width;
+ intel->scale_units[1][1] = pMask->drawable.height;
composite_op->is_affine |=
- i830_transform_is_affine(pI830->transform[1]);
+ i830_transform_is_affine(intel->transform[1]);
}
if (pMask) {
@@ -1609,8 +1609,8 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
static drm_intel_bo *i965_get_vb_space(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
- struct gen4_render_state *render_state = pI830->gen4_render_state;
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
+ struct gen4_render_state *render_state = intel->gen4_render_state;
/* If the vertex buffer is too full, then we free the old and a new one
* gets made.
@@ -1624,7 +1624,7 @@ static drm_intel_bo *i965_get_vb_space(ScrnInfoPtr pScrn)
/* Alloc a new vertex buffer if necessary. */
if (render_state->vertex_buffer_bo == NULL) {
render_state->vertex_buffer_bo =
- drm_intel_bo_alloc(pI830->bufmgr, "vb",
+ drm_intel_bo_alloc(intel->bufmgr, "vb",
sizeof(gen4_vertex_buffer), 4096);
render_state->vb_offset = 0;
}
@@ -1638,8 +1638,8 @@ i965_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
int dstX, int dstY, int w, int h)
{
ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
- I830Ptr pI830 = I830PTR(pScrn);
- struct gen4_render_state *render_state = pI830->gen4_render_state;
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
+ struct gen4_render_state *render_state = intel->gen4_render_state;
Bool has_mask;
float src_x[3], src_y[3], src_w[3], mask_x[3], mask_y[3], mask_w[3];
int i;
@@ -1649,70 +1649,70 @@ i965_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
if (is_affine) {
if (!i830_get_transformed_coordinates(srcX, srcY,
- pI830->transform[0],
+ intel->transform[0],
&src_x[0], &src_y[0]))
return;
if (!i830_get_transformed_coordinates(srcX, srcY + h,
- pI830->transform[0],
+ intel->transform[0],
&src_x[1], &src_y[1]))
return;
if (!i830_get_transformed_coordinates(srcX + w, srcY + h,
- pI830->transform[0],
+ intel->transform[0],
&src_x[2], &src_y[2]))
return;
} else {
if (!i830_get_transformed_coordinates_3d(srcX, srcY,
- pI830->transform[0],
+ intel->transform[0],
&src_x[0], &src_y[0],
&src_w[0]))
return;
if (!i830_get_transformed_coordinates_3d(srcX, srcY + h,
- pI830->transform[0],
+ intel->transform[0],
&src_x[1], &src_y[1],
&src_w[1]))
return;
if (!i830_get_transformed_coordinates_3d(srcX + w, srcY + h,
- pI830->transform[0],
+ intel->transform[0],
&src_x[2], &src_y[2],
&src_w[2]))
return;
}
- if (pI830->scale_units[1][0] == -1 || pI830->scale_units[1][1] == -1) {
+ if (intel->scale_units[1][0] == -1 || intel->scale_units[1][1] == -1) {
has_mask = FALSE;
} else {
has_mask = TRUE;
if (is_affine) {
if (!i830_get_transformed_coordinates(maskX, maskY,
- pI830->
+ intel->
transform[1],
&mask_x[0],
&mask_y[0]))
return;
if (!i830_get_transformed_coordinates(maskX, maskY + h,
- pI830->
+ intel->
transform[1],
&mask_x[1],
&mask_y[1]))
return;
if (!i830_get_transformed_coordinates
- (maskX + w, maskY + h, pI830->transform[1],
+ (maskX + w, maskY + h, intel->transform[1],
&mask_x[2], &mask_y[2]))
return;
} else {
if (!i830_get_transformed_coordinates_3d(maskX, maskY,
- pI830->
+ intel->
transform[1],
&mask_x[0],
&mask_y[0],
&mask_w[0]))
return;
if (!i830_get_transformed_coordinates_3d
- (maskX, maskY + h, pI830->transform[1], &mask_x[1],
+ (maskX, maskY + h, intel->transform[1], &mask_x[1],
&mask_y[1], &mask_w[1]))
return;
if (!i830_get_transformed_coordinates_3d
- (maskX + w, maskY + h, pI830->transform[1],
+ (maskX + w, maskY + h, intel->transform[1],
&mask_x[2], &mask_y[2], &mask_w[2]))
return;
}
@@ -1725,13 +1725,13 @@ i965_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
/* rect (x2,y2) */
vb[i++] = (float)(dstX + w);
vb[i++] = (float)(dstY + h);
- vb[i++] = src_x[2] / pI830->scale_units[0][0];
- vb[i++] = src_y[2] / pI830->scale_units[0][1];
+ vb[i++] = src_x[2] / intel->scale_units[0][0];
+ vb[i++] = src_y[2] / intel->scale_units[0][1];
if (!is_affine)
vb[i++] = src_w[2];
if (has_mask) {
- vb[i++] = mask_x[2] / pI830->scale_units[1][0];
- vb[i++] = mask_y[2] / pI830->scale_units[1][1];
+ vb[i++] = mask_x[2] / intel->scale_units[1][0];
+ vb[i++] = mask_y[2] / intel->scale_units[1][1];
if (!is_affine)
vb[i++] = mask_w[2];
}
@@ -1739,13 +1739,13 @@ i965_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
/* rect (x1,y2) */
vb[i++] = (float)dstX;
vb[i++] = (float)(dstY + h);
- vb[i++] = src_x[1] / pI830->scale_units[0][0];
- vb[i++] = src_y[1] / pI830->scale_units[0][1];
+ vb[i++] = src_x[1] / intel->scale_units[0][0];
+ vb[i++] = src_y[1] / intel->scale_units[0][1];
if (!is_affine)
vb[i++] = src_w[1];
if (has_mask) {
- vb[i++] = mask_x[1] / pI830->scale_units[1][0];
- vb[i++] = mask_y[1] / pI830->scale_units[1][1];
+ vb[i++] = mask_x[1] / intel->scale_units[1][0];
+ vb[i++] = mask_y[1] / intel->scale_units[1][1];
if (!is_affine)
vb[i++] = mask_w[1];
}
@@ -1753,13 +1753,13 @@ i965_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
/* rect (x1,y1) */
vb[i++] = (float)dstX;
vb[i++] = (float)dstY;
- vb[i++] = src_x[0] / pI830->scale_units[0][0];
- vb[i++] = src_y[0] / pI830->scale_units[0][1];
+ vb[i++] = src_x[0] / intel->scale_units[0][0];
+ vb[i++] = src_y[0] / intel->scale_units[0][1];
if (!is_affine)
vb[i++] = src_w[0];
if (has_mask) {
- vb[i++] = mask_x[0] / pI830->scale_units[1][0];
- vb[i++] = mask_y[0] / pI830->scale_units[1][1];
+ vb[i++] = mask_x[0] / intel->scale_units[1][0];
+ vb[i++] = mask_y[0] / intel->scale_units[1][1];
if (!is_affine)
vb[i++] = mask_w[0];
}
@@ -1783,7 +1783,7 @@ i965_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0,
render_state->vb_offset * 4);
- if (IS_IGDNG(pI830))
+ if (IS_IGDNG(intel))
OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0,
render_state->vb_offset * 4 + i * 4);
else
@@ -1810,8 +1810,8 @@ i965_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
void i965_batch_flush_notify(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
- struct gen4_render_state *render_state = pI830->gen4_render_state;
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
+ struct gen4_render_state *render_state = intel->gen4_render_state;
/* Once a batch is emitted, we never want to map again any buffer
* object being referenced by that batch, (which would be very
@@ -1829,22 +1829,22 @@ void i965_batch_flush_notify(ScrnInfoPtr pScrn)
*/
void gen4_render_state_init(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
struct gen4_render_state *render_state;
int i, j, k, l, m;
drm_intel_bo *sf_kernel_bo, *sf_kernel_mask_bo;
drm_intel_bo *border_color_bo;
- if (pI830->gen4_render_state == NULL)
- pI830->gen4_render_state = calloc(sizeof(*render_state), 1);
+ if (intel->gen4_render_state == NULL)
+ intel->gen4_render_state = calloc(sizeof(*render_state), 1);
- render_state = pI830->gen4_render_state;
+ render_state = intel->gen4_render_state;
render_state->vb_offset = 0;
render_state->vs_state_bo = gen4_create_vs_unit_state(pScrn);
/* Set up the two SF states (one for blending with a mask, one without) */
- if (IS_IGDNG(pI830)) {
+ if (IS_IGDNG(intel)) {
sf_kernel_bo = intel_bo_alloc_for_data(pScrn,
sf_kernel_static_gen5,
sizeof
@@ -1872,7 +1872,7 @@ void gen4_render_state_init(ScrnInfoPtr pScrn)
drm_intel_bo_unreference(sf_kernel_mask_bo);
for (m = 0; m < WM_KERNEL_COUNT; m++) {
- if (IS_IGDNG(pI830))
+ if (IS_IGDNG(intel))
render_state->wm_kernel_bo[m] =
intel_bo_alloc_for_data(pScrn,
wm_kernels_gen5[m].data,
@@ -1903,7 +1903,7 @@ void gen4_render_state_init(ScrnInfoPtr pScrn)
border_color_bo);
for (m = 0; m < WM_KERNEL_COUNT; m++) {
- if (IS_IGDNG(pI830))
+ if (IS_IGDNG(intel))
render_state->
wm_state_bo[m][i][j]
[k][l] =
@@ -1947,8 +1947,8 @@ void gen4_render_state_init(ScrnInfoPtr pScrn)
*/
void gen4_render_state_cleanup(ScrnInfoPtr pScrn)
{
- I830Ptr pI830 = I830PTR(pScrn);
- struct gen4_render_state *render_state = pI830->gen4_render_state;
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
+ struct gen4_render_state *render_state = intel->gen4_render_state;
int i, j, k, l, m;
gen4_composite_op *composite_op = &render_state->composite_op;
@@ -1975,6 +1975,6 @@ void gen4_render_state_cleanup(ScrnInfoPtr pScrn)
drm_intel_bo_unreference(render_state->cc_state_bo);
drm_intel_bo_unreference(render_state->sip_kernel_bo);
- free(pI830->gen4_render_state);
- pI830->gen4_render_state = NULL;
+ free(intel->gen4_render_state);
+ intel->gen4_render_state = NULL;
}
diff --git a/src/i965_video.c b/src/i965_video.c
index 881554c9..b35979bb 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -157,7 +157,7 @@ static struct {
static void brw_debug(ScrnInfoPtr pScrn, char *when)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
int i;
uint32_t v;
@@ -178,7 +178,7 @@ static void brw_debug(ScrnInfoPtr pScrn, char *when)
static void i965_pre_draw_debug(ScrnInfoPtr scrn)
{
#if 0
- I830Ptr pI830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
#endif
#if 0
@@ -229,7 +229,7 @@ static void i965_pre_draw_debug(ScrnInfoPtr scrn)
static void i965_post_draw_debug(ScrnInfoPtr scrn)
{
#if 0
- I830Ptr pI830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
#endif
#if 0
@@ -340,12 +340,12 @@ static void i965_post_draw_debug(ScrnInfoPtr scrn)
#define URB_CS_ENTRY_SIZE 0
static int
-intel_alloc_and_map(I830Ptr i830, char *name, int size,
+intel_alloc_and_map(intel_screen_private *intel, char *name, int size,
drm_intel_bo ** bop, void *virtualp)
{
drm_intel_bo *bo;
- bo = drm_intel_bo_alloc(i830->bufmgr, name, size, 4096);
+ bo = drm_intel_bo_alloc(intel->bufmgr, name, size, 4096);
if (!bo)
return -1;
if (drm_intel_bo_map(bo, TRUE) != 0) {
@@ -361,19 +361,19 @@ intel_alloc_and_map(I830Ptr i830, char *name, int size,
static drm_intel_bo *i965_create_dst_surface_state(ScrnInfoPtr scrn,
PixmapPtr pixmap)
{
- I830Ptr pI830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
struct brw_surface_state *dest_surf_state;
drm_intel_bo *pixmap_bo = i830_get_pixmap_bo(pixmap);
drm_intel_bo *surf_bo;
- if (intel_alloc_and_map(pI830, "textured video surface state", 4096,
+ if (intel_alloc_and_map(intel, "textured video surface state", 4096,
&surf_bo, &dest_surf_state) != 0)
return NULL;
dest_surf_state->ss0.surface_type = BRW_SURFACE_2D;
dest_surf_state->ss0.data_return_format =
BRW_SURFACERETURNFORMAT_FLOAT32;
- if (pI830->cpp == 2) {
+ if (intel->cpp == 2) {
dest_surf_state->ss0.surface_format =
BRW_SURFACEFORMAT_B5G6R5_UNORM;
} else {
@@ -414,11 +414,11 @@ static drm_intel_bo *i965_create_src_surface_state(ScrnInfoPtr scrn,
int src_pitch,
uint32_t src_surf_format)
{
- I830Ptr pI830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
drm_intel_bo *surface_bo;
struct brw_surface_state *src_surf_state;
- if (intel_alloc_and_map(pI830, "textured video surface state", 4096,
+ if (intel_alloc_and_map(intel, "textured video surface state", 4096,
&surface_bo, &src_surf_state) != 0)
return NULL;
@@ -459,14 +459,14 @@ static drm_intel_bo *i965_create_binding_table(ScrnInfoPtr scrn,
drm_intel_bo ** surf_bos,
int n_surf)
{
- I830Ptr pI830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
drm_intel_bo *bind_bo;
uint32_t *binding_table;
int i;
/* Set up a binding table for our surfaces. Only the PS will use it */
- if (intel_alloc_and_map(pI830, "textured video binding table", 4096,
+ if (intel_alloc_and_map(intel, "textured video binding table", 4096,
&bind_bo, &binding_table) != 0)
return NULL;
@@ -481,11 +481,11 @@ static drm_intel_bo *i965_create_binding_table(ScrnInfoPtr scrn,
static drm_intel_bo *i965_create_sampler_state(ScrnInfoPtr scrn)
{
- I830Ptr pI830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
drm_intel_bo *sampler_bo;
struct brw_sampler_state *sampler_state;
- if (intel_alloc_and_map(pI830, "textured video sampler state", 4096,
+ if (intel_alloc_and_map(intel, "textured video sampler state", 4096,
&sampler_bo, &sampler_state) != 0)
return NULL;
@@ -501,16 +501,16 @@ static drm_intel_bo *i965_create_sampler_state(ScrnInfoPtr scrn)
static drm_intel_bo *i965_create_vs_state(ScrnInfoPtr scrn)
{
- I830Ptr pI830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
drm_intel_bo *vs_bo;
struct brw_vs_unit_state *vs_state;
- if (intel_alloc_and_map(pI830, "textured video vs state", 4096,
+ if (intel_alloc_and_map(intel, "textured video vs state", 4096,
&vs_bo, &vs_state) != 0)
return NULL;
/* Set up the vertex shader to be disabled (passthrough) */
- if (IS_IGDNG(pI830))
+ if (IS_IGDNG(intel))
vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES >> 2;
else
vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
@@ -526,10 +526,10 @@ static drm_intel_bo *i965_create_program(ScrnInfoPtr scrn,
const uint32_t * program,
unsigned int program_size)
{
- I830Ptr pI830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
drm_intel_bo *prog_bo;
- prog_bo = drm_intel_bo_alloc(pI830->bufmgr, "textured video program",
+ prog_bo = drm_intel_bo_alloc(intel->bufmgr, "textured video program",
program_size, 4096);
if (!prog_bo)
return NULL;
@@ -541,11 +541,11 @@ static drm_intel_bo *i965_create_program(ScrnInfoPtr scrn,
static drm_intel_bo *i965_create_sf_state(ScrnInfoPtr scrn)
{
- I830Ptr pI830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
drm_intel_bo *sf_bo, *kernel_bo;
struct brw_sf_unit_state *sf_state;
- if (IS_IGDNG(pI830))
+ if (IS_IGDNG(intel))
kernel_bo =
i965_create_program(scrn, &sf_kernel_static_gen5[0][0],
sizeof(sf_kernel_static_gen5));
@@ -556,7 +556,7 @@ static drm_intel_bo *i965_create_sf_state(ScrnInfoPtr scrn)
if (!kernel_bo)
return NULL;
- if (intel_alloc_and_map(pI830, "textured video sf state", 4096,
+ if (intel_alloc_and_map(intel, "textured video sf state", 4096,
&sf_bo, &sf_state) != 0) {
drm_intel_bo_unreference(kernel_bo);
return NULL;
@@ -605,12 +605,12 @@ static drm_intel_bo *i965_create_wm_state(ScrnInfoPtr scrn,
drm_intel_bo * sampler_bo,
Bool is_packed)
{
- I830Ptr pI830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
drm_intel_bo *wm_bo, *kernel_bo;
struct brw_wm_unit_state *wm_state;
if (is_packed) {
- if (IS_IGDNG(pI830))
+ if (IS_IGDNG(intel))
kernel_bo =
i965_create_program(scrn,
&ps_kernel_packed_static_gen5[0]
@@ -624,7 +624,7 @@ static drm_intel_bo *i965_create_wm_state(ScrnInfoPtr scrn,
sizeof
(ps_kernel_packed_static));
} else {
- if (IS_IGDNG(pI830))
+ if (IS_IGDNG(intel))
kernel_bo =
i965_create_program(scrn,
&ps_kernel_planar_static_gen5[0]
@@ -642,7 +642,7 @@ static drm_intel_bo *i965_create_wm_state(ScrnInfoPtr scrn,
return NULL;
if (intel_alloc_and_map
- (pI830, "textured video wm state", sizeof(*wm_state), &wm_bo,
+ (intel, "textured video wm state", sizeof(*wm_state), &wm_bo,
&wm_state)) {
drm_intel_bo_unreference(kernel_bo);
return NULL;
@@ -662,7 +662,7 @@ static drm_intel_bo *i965_create_wm_state(ScrnInfoPtr scrn,
/* binding table entry count is only used for prefetching, and it has to
* be set 0 for IGDNG
*/
- if (IS_IGDNG(pI830))
+ if (IS_IGDNG(intel))
wm_state->thread1.binding_table_entry_count = 0;
/* Though we never use the scratch space in our WM kernel, it has to be
@@ -680,7 +680,7 @@ static drm_intel_bo *i965_create_wm_state(ScrnInfoPtr scrn,
intel_emit_reloc(wm_bo, offsetof(struct brw_wm_unit_state, wm4),
sampler_bo, 0,
I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5;
- if (IS_IGDNG(pI830))
+ if (IS_IGDNG(intel))
wm_state->wm4.sampler_count = 0;
else
wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
@@ -698,11 +698,11 @@ static drm_intel_bo *i965_create_wm_state(ScrnInfoPtr scrn,
static drm_intel_bo *i965_create_cc_vp_state(ScrnInfoPtr scrn)
{
- I830Ptr pI830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
drm_intel_bo *cc_vp_bo;
struct brw_cc_viewport *cc_viewport;
- if (intel_alloc_and_map(pI830, "textured video cc viewport", 4096,
+ if (intel_alloc_and_map(intel, "textured video cc viewport", 4096,
&cc_vp_bo, &cc_viewport) != 0)
return NULL;
@@ -715,7 +715,7 @@ static drm_intel_bo *i965_create_cc_vp_state(ScrnInfoPtr scrn)
static drm_intel_bo *i965_create_cc_state(ScrnInfoPtr scrn)
{
- I830Ptr pI830 = I830PTR(scrn);
+ intel_screen_private *intel = intel_get_screen_private(scrn);
drm_intel_bo *cc_bo, *cc_vp_bo;
struct brw_cc_unit_state *cc_state;
@@ -724,7 +724,7 @@ static drm_intel_bo *i965_create_cc_state(ScrnInfoPtr scrn)
return NULL;
if (intel_alloc_and_map
- (pI830, "textured video cc state", sizeof(*cc_state), &cc_bo,
+ (intel, "textured video cc state", sizeof(*cc_state), &cc_bo,
&cc_state) != 0) {
drm_intel_bo_unreference(cc_vp_bo);
return NULL;
@@ -757,7 +757,7 @@ static drm_intel_bo *i965_create_cc_state(ScrnInfoPtr scrn)
static void
i965_emit_video_setup(ScrnInfoPtr pScrn, drm_intel_bo * bind_bo, int n_src_surf)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
int urb_vs_start, urb_vs_size;
int urb_gs_start, urb_gs_size;
int urb_clip_start, urb_clip_size;
@@ -766,7 +766,7 @@ i965_emit_video_setup(ScrnInfoPtr pScrn, drm_intel_bo * bind_bo, int n_src_surf)
int pipe_ctl;
IntelEmitInvarientState(pScrn);
- pI830->last_3d = LAST_3D_VIDEO;
+ intel->last_3d = LAST_3D_VIDEO;
urb_vs_start = 0;
urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE;
@@ -787,12 +787,12 @@ i965_emit_video_setup(ScrnInfoPtr pScrn, drm_intel_bo * bind_bo, int n_src_surf)
ADVANCE_BATCH();
/* brw_debug (pScrn, "before base address modify"); */
- if (IS_IGDNG(pI830))
+ if (IS_IGDNG(intel))
BEGIN_BATCH(14);
else
BEGIN_BATCH(12);
/* Match Mesa driver setup */
- if (IS_G4X(pI830) || IS_IGDNG(pI830))
+ if (IS_G4X(intel) || IS_IGDNG(intel))
OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
else
OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
@@ -805,7 +805,7 @@ i965_emit_video_setup(ScrnInfoPtr pScrn, drm_intel_bo * bind_bo, int n_src_surf)
/* Zero out the two base address registers so all offsets are
* absolute
*/
- if (IS_IGDNG(pI830)) {
+ if (IS_IGDNG(intel)) {
OUT_BATCH(BRW_STATE_BASE_ADDRESS | 6);
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */
@@ -831,7 +831,7 @@ i965_emit_video_setup(ScrnInfoPtr pScrn, drm_intel_bo * bind_bo, int n_src_surf)
/* Set system instruction pointer */
OUT_BATCH(BRW_STATE_SIP | 0);
/* system instruction pointer */
- OUT_RELOC(pI830->video.gen4_sip_kernel_bo,
+ OUT_RELOC(intel->video.gen4_sip_kernel_bo,
I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
OUT_BATCH(MI_NOOP);
@@ -839,7 +839,7 @@ i965_emit_video_setup(ScrnInfoPtr pScrn, drm_intel_bo * bind_bo, int n_src_surf)
/* brw_debug (pScrn, "after base address modify"); */
- if (IS_IGDNG(pI830))
+ if (IS_IGDNG(intel))
pipe_ctl = BRW_PIPE_CONTROL_NOWRITE;
else
pipe_ctl = BRW_PIPE_CONTROL_NOWRITE | BRW_PIPE_CONTROL_IS_FLUSH;
@@ -885,19 +885,19 @@ i965_emit_video_setup(ScrnInfoPtr pScrn, drm_intel_bo * bind_bo, int n_src_surf)
/* Set the pointers to the 3d pipeline state */
OUT_BATCH(BRW_3DSTATE_PIPELINED_POINTERS | 5);
- OUT_RELOC(pI830->video.gen4_vs_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+ OUT_RELOC(intel->video.gen4_vs_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
/* disable GS, resulting in passthrough */
OUT_BATCH(BRW_GS_DISABLE);
/* disable CLIP, resulting in passthrough */
OUT_BATCH(BRW_CLIP_DISABLE);
- OUT_RELOC(pI830->video.gen4_sf_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+ OUT_RELOC(intel->video.gen4_sf_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
if (n_src_surf == 1)
- OUT_RELOC(pI830->video.gen4_wm_packed_bo,
+ OUT_RELOC(intel->video.gen4_wm_packed_bo,
I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
else
- OUT_RELOC(pI830->video.gen4_wm_planar_bo,
+ OUT_RELOC(intel->video.gen4_wm_planar_bo,
I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
- OUT_RELOC(pI830->video.gen4_cc_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+ OUT_RELOC(intel->video.gen4_cc_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
/* URB fence */
OUT_BATCH(BRW_URB_FENCE |
@@ -916,7 +916,7 @@ i965_emit_video_setup(ScrnInfoPtr pScrn, drm_intel_bo * bind_bo, int n_src_surf)
/* Set up our vertex elements, sourced from the single vertex buffer. */
- if (IS_IGDNG(pI830)) {
+ if (IS_IGDNG(intel)) {
OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | 3);
/* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
@@ -984,7 +984,7 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
short src_w, short src_h,
short drw_w, short drw_h, PixmapPtr pPixmap)
{
- I830Ptr pI830 = I830PTR(pScrn);
+ intel_screen_private *intel = intel_get_screen_private(pScrn);
BoxPtr pbox;
int nbox, dxo, dyo, pix_xoff, pix_yoff;
float src_scale_x, src_scale_y;
@@ -1087,55 +1087,55 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
if (!bind_bo)
return;
- if (pI830->video.gen4_sampler_bo == NULL)
- pI830->video.gen4_sampler_bo = i965_create_sampler_state(pScrn);
- if (pI830->video.gen4_sip_kernel_bo == NULL) {
- pI830->video.gen4_sip_kernel_bo =
+ if (intel->video.gen4_sampler_bo == NULL)
+ intel->video.gen4_sampler_bo = i965_create_sampler_state(pScrn);
+ if (intel->video.gen4_sip_kernel_bo == NULL) {
+ intel->video.gen4_sip_kernel_bo =
i965_create_program(pScrn, &sip_kernel_static[0][0],
sizeof(sip_kernel_static));
- if (!pI830->video.gen4_sip_kernel_bo) {
+ if (!intel->video.gen4_sip_kernel_bo) {
drm_intel_bo_unreference(bind_bo);
return;
}
}
- if (pI830->video.gen4_vs_bo == NULL) {
- pI830->video.gen4_vs_bo = i965_create_vs_state(pScrn);
- if (!pI830->video.gen4_vs_bo) {
+ if (intel->video.gen4_vs_bo == NULL) {
+ intel->video.gen4_vs_bo = i965_create_vs_state(pScrn);
+ if (!intel->video.gen4_vs_bo) {
drm_intel_bo_unreference(bind_bo);
return;
}
}
- if (pI830->video.gen4_sf_bo == NULL) {
- pI830->video.gen4_sf_bo = i965_create_sf_state(pScrn);
- if (!pI830->video.gen4_sf_bo) {
+ if (intel->video.gen4_sf_bo == NULL) {
+ intel->video.gen4_sf_bo = i965_create_sf_state(pScrn);
+ if (!intel->video.gen4_sf_bo) {
drm_intel_bo_unreference(bind_bo);
return;
}
}
- if (pI830->video.gen4_wm_packed_bo == NULL) {
- pI830->video.gen4_wm_packed_bo =
- i965_create_wm_state(pScrn, pI830->video.gen4_sampler_bo,
+ if (intel->video.gen4_wm_packed_bo == NULL) {
+ intel->video.gen4_wm_packed_bo =
+ i965_create_wm_state(pScrn, intel->video.gen4_sampler_bo,
TRUE);
- if (!pI830->video.gen4_wm_packed_bo) {
+ if (!intel->video.gen4_wm_packed_bo) {
drm_intel_bo_unreference(bind_bo);
return;
}
}
- if (pI830->video.gen4_wm_planar_bo == NULL) {
- pI830->video.gen4_wm_planar_bo =
- i965_create_wm_state(pScrn, pI830->video.gen4_sampler_bo,
+ if (intel->video.gen4_wm_planar_bo == NULL) {
+ intel->video.gen4_wm_planar_bo =
+ i965_create_wm_state(pScrn, intel->video.gen4_sampler_bo,
FALSE);
- if (!pI830->video.gen4_wm_planar_bo) {
+ if (!intel->video.gen4_wm_planar_bo) {
drm_intel_bo_unreference(bind_bo);
return;
}
}
- if (pI830->video.gen4_cc_bo == NULL) {
- pI830->video.gen4_cc_bo = i965_create_cc_state(pScrn);
- if (!pI830->video.gen4_cc_bo) {
+ if (intel->video.gen4_cc_bo == NULL) {
+ intel->video.gen4_cc_bo = i965_create_cc_state(pScrn);
+ if (!intel->video.gen4_cc_bo) {
drm_intel_bo_unreference(bind_bo);
return;
}
@@ -1171,20 +1171,20 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
float *vb;
drm_intel_bo *bo_table[] = {
NULL, /* vb_bo */
- pI830->batch_bo,
+ intel->batch_bo,
bind_bo,
- pI830->video.gen4_sampler_bo,
- pI830->video.gen4_sip_kernel_bo,
- pI830->video.gen4_vs_bo,
- pI830->video.gen4_sf_bo,
- pI830->video.gen4_wm_packed_bo,
- pI830->video.gen4_wm_planar_bo,
- pI830->video.gen4_cc_bo,
+ intel->video.gen4_sampler_bo,
+ intel->video.gen4_sip_kernel_bo,
+ intel->video.gen4_vs_bo,
+ intel->video.gen4_sf_bo,
+ intel->video.gen4_wm_packed_bo,
+ intel->video.gen4_wm_planar_bo,
+ intel->video.gen4_cc_bo,
};
pbox++;
- if (intel_alloc_and_map(pI830, "textured video vb", 4096,
+ if (intel_alloc_and_map(intel, "textured video vb", 4096,
&vb_bo, &vb) != 0)
break;
bo_table[0] = vb_bo;
@@ -1207,7 +1207,7 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
drm_intel_bo_unmap(vb_bo);
- if (!IS_IGDNG(pI830))
+ if (!IS_IGDNG(intel))
i965_pre_draw_debug(pScrn);
/* If this command won't fit in the current batch, flush.
@@ -1230,7 +1230,7 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
OUT_BATCH((0 << VB0_BUFFER_INDEX_SHIFT) |
VB0_VERTEXDATA | ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
- if (IS_IGDNG(pI830))
+ if (IS_IGDNG(intel))
OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0,
(vb_bo->offset + i) * 4);
else
@@ -1251,7 +1251,7 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
drm_intel_bo_unreference(vb_bo);
- if (!IS_IGDNG(pI830))
+ if (!IS_IGDNG(intel))
i965_post_draw_debug(pScrn);
}
@@ -1266,22 +1266,22 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
void i965_free_video(ScrnInfoPtr scrn)
{
- I830Ptr pI830 = I830PTR(scrn);
-
- drm_intel_bo_unreference(pI830->video.gen4_vs_bo);
- pI830->video.gen4_vs_bo = NULL;
- drm_intel_bo_unreference(pI830->video.gen4_sf_bo);
- pI830->video.gen4_sf_bo = NULL;
- drm_intel_bo_unreference(pI830->video.gen4_cc_bo);
- pI830->video.gen4_cc_bo = NULL;
- drm_intel_bo_unreference(pI830->video.gen4_wm_packed_bo);
- pI830->video.gen4_wm_packed_bo = NULL;
- drm_intel_bo_unreference(pI830->video.gen4_wm_planar_bo);
- pI830->video.gen4_wm_planar_bo = NULL;
- drm_intel_bo_unreference(pI830->video.gen4_cc_vp_bo);
- pI830->video.gen4_cc_vp_bo = NULL;
- drm_intel_bo_unreference(pI830->video.gen4_sampler_bo);
- pI830->video.gen4_sampler_bo = NULL;
- drm_intel_bo_unreference(pI830->video.gen4_sip_kernel_bo);
- pI830->video.gen4_sip_kernel_bo = NULL;
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ drm_intel_bo_unreference(intel->video.gen4_vs_bo);
+ intel->video.gen4_vs_bo = NULL;
+ drm_intel_bo_unreference(intel->video.gen4_sf_bo);
+ intel->video.gen4_sf_bo = NULL;
+ drm_intel_bo_unreference(intel->video.gen4_cc_bo);
+ intel->video.gen4_cc_bo = NULL;
+ drm_intel_bo_unreference(intel->video.gen4_wm_packed_bo);
+ intel->video.gen4_wm_packed_bo = NULL;
+ drm_intel_bo_unreference(intel->video.gen4_wm_planar_bo);
+ intel->video.gen4_wm_planar_bo = NULL;
+ drm_intel_bo_unreference(intel->video.gen4_cc_vp_bo);
+ intel->video.gen4_cc_vp_bo = NULL;
+ drm_intel_bo_unreference(intel->video.gen4_sampler_bo);
+ intel->video.gen4_sampler_bo = NULL;
+ drm_intel_bo_unreference(intel->video.gen4_sip_kernel_bo);
+ intel->video.gen4_sip_kernel_bo = NULL;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 14:38:30 +0000