diff options
| author | Zhenyu Wang <zhenyu.z.wang@intel.com> | 2008-01-09 21:27:42 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyu.z.wang@intel.com> | 2008-01-09 21:27:42 +0800 |
| commit | 2f0c0427dc4113bac64cda07c6365df1f0637697 (patch) | |
| tree | 429649e41e436b2719936149de9138a084adb5df /src | |
| parent | 139e9affdd49dcbe08e260a0a2bd001de16566e6 (diff) | |
Update PIPELINE_SELECT instruction and surface state format for new chipset
Diffstat (limited to 'src')
| -rw-r--r-- | src/brw_structs.h | 12 | ||||
| -rw-r--r-- | src/i810_reg.h | 2 | ||||
| -rw-r--r-- | src/i965_render.c | 6 | ||||
| -rw-r--r-- | src/i965_video.c | 5 |
4 files changed, 20 insertions, 5 deletions
diff --git a/src/brw_structs.h b/src/brw_structs.h index 28d8e127..d4fc5c67 100644 --- a/src/brw_structs.h +++ b/src/brw_structs.h @@ -832,9 +832,8 @@ struct brw_wm_unit_state unsigned int program_computes_depth:1; unsigned int program_uses_killpixel:1; unsigned int legacy_line_rast: 1; - unsigned int pad1:1; - unsigned int max_threads:6; - unsigned int pad2:1; + unsigned int transposed_urb_read:1; + unsigned int max_threads:7; } wm5; float global_depth_offset_constant; @@ -977,6 +976,13 @@ struct brw_surface_state unsigned int min_array_elt:9; unsigned int min_lod:4; } ss4; + + struct { + unsigned int pad:20; + unsigned int y_offset:4; + unsigned int pad2:1; + unsigned int x_offset:7; + } ss5; }; diff --git a/src/i810_reg.h b/src/i810_reg.h index 26f9db48..bed3901e 100644 --- a/src/i810_reg.h +++ b/src/i810_reg.h @@ -2284,6 +2284,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define BRW_STATE_SIP BRW_3D(0, 1, 2) #define BRW_PIPELINE_SELECT BRW_3D(0, 1, 4) +#define NEW_PIPELINE_SELECT BRW_3D(1, 1, 4) + #define BRW_MEDIA_STATE_POINTERS BRW_3D(2, 0, 0) #define BRW_MEDIA_OBJECT BRW_3D(2, 1, 0) diff --git a/src/i965_render.c b/src/i965_render.c index ad3b53ef..4b1d7f3e 100644 --- a/src/i965_render.c +++ b/src/i965_render.c @@ -907,6 +907,7 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture, src_sampler_offset) >> 5; wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */ wm_state->wm5.max_threads = PS_MAX_THREADS - 1; + wm_state->wm5.transposed_urb_read = 0; wm_state->wm5.thread_dispatch_enable = 1; /* just use 16-pixel dispatch (4 subspans), don't need to change kernel * start point @@ -933,7 +934,10 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture, BEGIN_LP_RING(12); /* Match Mesa driver setup */ - OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D); + if (IS_IGD_GM(pI830)) + OUT_RING(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D); + else + OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D); OUT_RING(BRW_CS_URB_STATE | 0); OUT_RING((0 << 4) | /* URB Entry Allocation Size */ diff --git a/src/i965_video.c b/src/i965_video.c index 03572703..928b52b7 100644 --- a/src/i965_video.c +++ b/src/i965_video.c @@ -509,7 +509,10 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id, { BEGIN_LP_RING(12); /* Match Mesa driver setup */ - OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D); + if (IS_IGD_GM(pI830)) + OUT_RING(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D); + else + OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D); /* Mesa does this. Who knows... */ OUT_RING(BRW_CS_URB_STATE | 0); |