diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2013-07-26 10:41:00 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2013-07-28 14:49:07 +0100 |
| commit | a84a9fcb5e1218f685e4469dbe00f8f29cc36bf5 (patch) | |
| tree | d7868cc95ded78bd65fadc5a72c43fdc825cd7b0 /src | |
| parent | 8afb5438f3479df39752cbda680c13d80f81f42f (diff) | |
intel: Remove the unused bridge PCI-IDs
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'src')
| -rw-r--r-- | src/intel_driver.h | 109 |
1 files changed, 22 insertions, 87 deletions
diff --git a/src/intel_driver.h b/src/intel_driver.h index 542a30a7..be433586 100644 --- a/src/intel_driver.h +++ b/src/intel_driver.h @@ -9,117 +9,52 @@ #define INTEL_VERSION_MINOR PACKAGE_VERSION_MINOR #define INTEL_VERSION_PATCH PACKAGE_VERSION_PATCHLEVEL -#define PCI_CHIP_I810 0x7121 -#define PCI_CHIP_I810_DC100 0x7123 -#define PCI_CHIP_I810_E 0x7125 -#define PCI_CHIP_I815 0x1132 -#define PCI_CHIP_I810_BRIDGE 0x7120 -#define PCI_CHIP_I810_DC100_BRIDGE 0x7122 -#define PCI_CHIP_I810_E_BRIDGE 0x7124 -#define PCI_CHIP_I815_BRIDGE 0x1130 - -#define PCI_CHIP_I830_M 0x3577 -#define PCI_CHIP_I830_M_BRIDGE 0x3575 - -#define PCI_CHIP_845_G 0x2562 -#define PCI_CHIP_845_G_BRIDGE 0x2560 - -#define PCI_CHIP_I854 0x358E -#define PCI_CHIP_I854_BRIDGE 0x358C - -#define PCI_CHIP_I855_GM 0x3582 -#define PCI_CHIP_I855_GM_BRIDGE 0x3580 - -#define PCI_CHIP_I865_G 0x2572 -#define PCI_CHIP_I865_G_BRIDGE 0x2570 - -#define PCI_CHIP_I915_G 0x2582 -#define PCI_CHIP_I915_G_BRIDGE 0x2580 - -#define PCI_CHIP_I915_GM 0x2592 -#define PCI_CHIP_I915_GM_BRIDGE 0x2590 - -#define PCI_CHIP_E7221_G 0x258A -/* Same as I915_G_BRIDGE */ -#define PCI_CHIP_E7221_G_BRIDGE 0x2580 - -#define PCI_CHIP_I945_G 0x2772 -#define PCI_CHIP_I945_G_BRIDGE 0x2770 - +#define PCI_CHIP_I810 0x7121 +#define PCI_CHIP_I810_DC100 0x7123 +#define PCI_CHIP_I810_E 0x7125 +#define PCI_CHIP_I815 0x1132 + +#define PCI_CHIP_I830_M 0x3577 +#define PCI_CHIP_845_G 0x2562 +#define PCI_CHIP_I854 0x358E +#define PCI_CHIP_I855_GM 0x3582 +#define PCI_CHIP_I865_G 0x2572 + +#define PCI_CHIP_I915_G 0x2582 +#define PCI_CHIP_I915_GM 0x2592 +#define PCI_CHIP_E7221_G 0x258A +#define PCI_CHIP_I945_G 0x2772 #define PCI_CHIP_I945_GM 0x27A2 -#define PCI_CHIP_I945_GM_BRIDGE 0x27A0 - -#define PCI_CHIP_I945_GME 0x27AE -#define PCI_CHIP_I945_GME_BRIDGE 0x27AC - -#define PCI_CHIP_PINEVIEW_M 0xA011 -#define PCI_CHIP_PINEVIEW_M_BRIDGE 0xA010 -#define PCI_CHIP_PINEVIEW_G 0xA001 -#define PCI_CHIP_PINEVIEW_G_BRIDGE 0xA000 +#define PCI_CHIP_I945_GME 0x27AE +#define PCI_CHIP_PINEVIEW_M 0xA011 +#define PCI_CHIP_PINEVIEW_G 0xA001 +#define PCI_CHIP_Q35_G 0x29B2 +#define PCI_CHIP_G33_G 0x29C2 +#define PCI_CHIP_Q33_G 0x29D2 #define PCI_CHIP_G35_G 0x2982 -#define PCI_CHIP_G35_G_BRIDGE 0x2980 - #define PCI_CHIP_I965_Q 0x2992 -#define PCI_CHIP_I965_Q_BRIDGE 0x2990 - #define PCI_CHIP_I965_G 0x29A2 -#define PCI_CHIP_I965_G_BRIDGE 0x29A0 - -#define PCI_CHIP_I946_GZ 0x2972 -#define PCI_CHIP_I946_GZ_BRIDGE 0x2970 - +#define PCI_CHIP_I946_GZ 0x2972 #define PCI_CHIP_I965_GM 0x2A02 -#define PCI_CHIP_I965_GM_BRIDGE 0x2A00 - #define PCI_CHIP_I965_GME 0x2A12 -#define PCI_CHIP_I965_GME_BRIDGE 0x2A10 - -#define PCI_CHIP_G33_G 0x29C2 -#define PCI_CHIP_G33_G_BRIDGE 0x29C0 - -#define PCI_CHIP_Q35_G 0x29B2 -#define PCI_CHIP_Q35_G_BRIDGE 0x29B0 - -#define PCI_CHIP_Q33_G 0x29D2 -#define PCI_CHIP_Q33_G_BRIDGE 0x29D0 - #define PCI_CHIP_GM45_GM 0x2A42 -#define PCI_CHIP_GM45_BRIDGE 0x2A40 - #define PCI_CHIP_G45_E_G 0x2E02 -#define PCI_CHIP_G45_E_G_BRIDGE 0x2E00 - #define PCI_CHIP_G45_G 0x2E22 -#define PCI_CHIP_G45_G_BRIDGE 0x2E20 - #define PCI_CHIP_Q45_G 0x2E12 -#define PCI_CHIP_Q45_G_BRIDGE 0x2E10 - #define PCI_CHIP_G41_G 0x2E32 -#define PCI_CHIP_G41_G_BRIDGE 0x2E30 - #define PCI_CHIP_B43_G 0x2E42 -#define PCI_CHIP_B43_G_BRIDGE 0x2E40 - #define PCI_CHIP_B43_G1 0x2E92 -#define PCI_CHIP_B43_G1_BRIDGE 0x2E90 #define PCI_CHIP_IRONLAKE_D_G 0x0042 -#define PCI_CHIP_IRONLAKE_D_G_BRIDGE 0x0040 - #define PCI_CHIP_IRONLAKE_M_G 0x0046 -#define PCI_CHIP_IRONLAKE_M_G_BRIDGE 0x0044 -#define PCI_CHIP_SANDYBRIDGE_BRIDGE 0x0100 /* Desktop */ #define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 #define PCI_CHIP_SANDYBRIDGE_GT2 0x0112 #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122 -#define PCI_CHIP_SANDYBRIDGE_BRIDGE_M 0x0104 /* Mobile */ #define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 #define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126 -#define PCI_CHIP_SANDYBRIDGE_BRIDGE_S 0x0108 /* Server */ #define PCI_CHIP_SANDYBRIDGE_S_GT 0x010A #define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 |