Check that batch buffers are atomic.

Since batch buffers are rarely emitted by themselves but as part of a
sequence of state and vertices, the whole sequence is emitted atomically.

Here we just enforce that batches are marked as being part of an atomic
sequence as appropriate.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

(Cherry picked from commit 67af5a99253b1295f8dc09b28863eb7dc8b59e1d).

11 files changed, 43 insertions, 32 deletions

diff --git a/src/i830_3d.c b/src/i830_3d.c
index c95a0b13..e83cb3f7 100644
--- a/src/i830_3d.c
+++ b/src/i830_3d.c
@@ -38,7 +38,7 @@ void I830EmitInvarientState(ScrnInfoPtr scrn)
 {
 	intel_screen_private *intel = intel_get_screen_private(scrn);
 
-	BEGIN_BATCH(58);
+	ATOMIC_BATCH(58);
 
 	OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(0));
 	OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(1));
diff --git a/src/i830_batchbuffer.c b/src/i830_batchbuffer.c
index 1d106406..22e1bb4f 100644
--- a/src/i830_batchbuffer.c
+++ b/src/i830_batchbuffer.c
@@ -169,6 +169,8 @@ void intel_batch_flush(ScrnInfoPtr scrn, Bool flushed)
 	intel_screen_private *intel = intel_get_screen_private(scrn);
 	int ret;
 
+	assert (!intel->in_batch_atomic);
+
 	if (intel->batch_used == 0)
 		return;
 
diff --git a/src/i830_batchbuffer.h b/src/i830_batchbuffer.h
index 82bf6112..51382286 100644
--- a/src/i830_batchbuffer.h
+++ b/src/i830_batchbuffer.h
@@ -135,11 +135,24 @@ do {									\
 	if (intel->batch_emitting != 0)					\
 		FatalError("%s: BEGIN_BATCH called without closing "	\
 			   "ADVANCE_BATCH\n", __FUNCTION__);		\
+	assert(!intel->in_batch_atomic);				\
 	intel_batch_require_space(scrn, intel, (n) * 4);		\
 	intel->batch_emitting = (n) * 4;				\
 	intel->batch_emit_start = intel->batch_used;			\
 } while (0)
 
+/* special-case variant for when we have preallocated space */
+#define ATOMIC_BATCH(n)							\
+do {									\
+	if (intel->batch_emitting != 0)					\
+		FatalError("%s: ATOMIC_BATCH called without closing "	\
+			   "ADVANCE_BATCH\n", __FUNCTION__);		\
+	assert(intel->in_batch_atomic);					\
+	assert(intel->batch_used + (n) * 4 <= intel->batch_atomic_limit); \
+	intel->batch_emitting = (n) * 4;				\
+	intel->batch_emit_start = intel->batch_used;			\
+} while (0)
+
 #define ADVANCE_BATCH() do {						\
 	if (intel->batch_emitting == 0)					\
 		FatalError("%s: ADVANCE_BATCH called with no matching "	\
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 5d25d5d9..c5ab8b6d 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2756,9 +2756,6 @@ I830ScreenInit(int scrnIndex, ScreenPtr screen, int argc, char **argv)
 	if (intel->XvEnabled)
 		I830InitVideo(screen);
 
-	/* Setup 3D engine, needed for rotation too */
-	IntelEmitInvarientState(scrn);
-
 #if defined(DRI2)
 	switch (intel->directRenderingType) {
 	case DRI_DRI2:
@@ -3007,9 +3004,8 @@ static Bool I830EnterVT(int scrnIndex, int flags)
 	*/
 	i830SetHotkeyControl(scrn, HOTKEY_DRIVER_NOTIFY);
 
-	/* Mark 3D state as being clobbered and setup the basics */
+	/* Mark all state as being clobbered. */
 	intel->last_3d = LAST_3D_OTHER;
-	IntelEmitInvarientState(scrn);
 
 	return TRUE;
 }
diff --git a/src/i830_render.c b/src/i830_render.c
index 24d644be..ee89950d 100644
--- a/src/i830_render.c
+++ b/src/i830_render.c
@@ -339,7 +339,7 @@ static void i830_texture_setup(PicturePtr picture, PixmapPtr pixmap, int unit)
 		else
 			format |= MAPSURF_32BIT;
 
-		BEGIN_BATCH(10);
+		ATOMIC_BATCH(10);
 		OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
 			  LOAD_TEXTURE_MAP(unit) | 4);
 		OUT_RELOC_PIXMAP(pixmap, I915_GEM_DOMAIN_SAMPLER, 0,
@@ -569,7 +569,7 @@ static void i830_emit_composite_state(ScrnInfoPtr scrn)
 	IntelEmitInvarientState(scrn);
 	intel->last_3d = LAST_3D_RENDER;
 
-	BEGIN_BATCH(21);
+	ATOMIC_BATCH(21);
 
 	OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
 	OUT_BATCH(BUF_3D_ID_COLOR_BACK | BUF_3D_USE_FENCE |
@@ -770,7 +770,7 @@ i830_emit_composite_primitive(PixmapPtr dest,
 
 	num_floats = 3 * per_vertex;
 
-	BEGIN_BATCH(1 + num_floats);
+	ATOMIC_BATCH(1 + num_floats);
 
 	OUT_BATCH(PRIM3D_INLINE | PRIM3D_RECTLIST | (num_floats - 1));
 	OUT_BATCH_F(intel->dst_coord_adjust + dstX + w);
diff --git a/src/i915_3d.c b/src/i915_3d.c
index e3b56741..517c6851 100644
--- a/src/i915_3d.c
+++ b/src/i915_3d.c
@@ -38,7 +38,7 @@ void I915EmitInvarientState(ScrnInfoPtr scrn)
 {
 	intel_screen_private *intel = intel_get_screen_private(scrn);
 
-	BEGIN_BATCH(24);
+	ATOMIC_BATCH(24);
 
 	OUT_BATCH(_3DSTATE_AA_CMD |
 		  AA_LINE_ECAAR_WIDTH_ENABLE |
diff --git a/src/i915_3d.h b/src/i915_3d.h
index 117712e5..500817f4 100644
--- a/src/i915_3d.h
+++ b/src/i915_3d.h
@@ -441,7 +441,7 @@ do {									\
 #define FS_END()							\
 do {									\
     int _i, _pad = (_cur_shader_commands & 0x1) ? 0 : 1;		\
-    BEGIN_BATCH(_cur_shader_commands * 3 + 1 + _pad);			\
+    ATOMIC_BATCH(_cur_shader_commands * 3 + 1 + _pad);			\
     OUT_BATCH(_3DSTATE_PIXEL_SHADER_PROGRAM |				\
 	     (_cur_shader_commands * 3 - 1));				\
     for (_i = 0; _i < _cur_shader_commands * 3; _i++)			\
diff --git a/src/i915_render.c b/src/i915_render.c
index 6a936bea..65fea784 100644
--- a/src/i915_render.c
+++ b/src/i915_render.c
@@ -438,7 +438,7 @@ static void i915_emit_composite_setup(ScrnInfoPtr scrn)
 	is_affine_mask = i830_transform_is_affine(intel->transform[1]);
 
 	if (mask == NULL) {
-		BEGIN_BATCH(10);
+		ATOMIC_BATCH(10);
 		OUT_BATCH(_3DSTATE_MAP_STATE | 3);
 		OUT_BATCH(0x00000001);	/* map 0 */
 		OUT_RELOC_PIXMAP(source, I915_GEM_DOMAIN_SAMPLER, 0, 0);
@@ -452,7 +452,7 @@ static void i915_emit_composite_setup(ScrnInfoPtr scrn)
 		OUT_BATCH(intel->samplerstate[2]);
 		ADVANCE_BATCH();
 	} else {
-		BEGIN_BATCH(16);
+		ATOMIC_BATCH(16);
 		OUT_BATCH(_3DSTATE_MAP_STATE | 6);
 		OUT_BATCH(0x00000003);	/* map 0,1 */
 		OUT_RELOC_PIXMAP(source, I915_GEM_DOMAIN_SAMPLER, 0, 0);
@@ -475,7 +475,7 @@ static void i915_emit_composite_setup(ScrnInfoPtr scrn)
 	{
 		uint32_t ss2;
 
-		BEGIN_BATCH(16);
+		ATOMIC_BATCH(16);
 		OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
 		OUT_BATCH(BUF_3D_ID_COLOR_BACK | BUF_3D_USE_FENCE |
 			  BUF_3D_PITCH(dst_pitch));
@@ -731,7 +731,7 @@ i915_emit_composite_primitive(PixmapPtr dest,
 
 	num_floats = 3 * per_vertex;
 
-	BEGIN_BATCH(1 + num_floats);
+	ATOMIC_BATCH(1 + num_floats);
 
 	OUT_BATCH(PRIM3D_INLINE | PRIM3D_RECTLIST | (num_floats - 1));
 	OUT_BATCH_F(intel->dst_coord_adjust + dstX + w);
diff --git a/src/i915_video.c b/src/i915_video.c
index e54bd9b4..4e4ec03a 100644
--- a/src/i915_video.c
+++ b/src/i915_video.c
@@ -75,7 +75,7 @@ I915DisplayVideoTextured(ScrnInfoPtr scrn,
 		IntelEmitInvarientState(scrn);
 		intel->last_3d = LAST_3D_VIDEO;
 
-		BEGIN_BATCH(20);
+		ATOMIC_BATCH(20);
 
 		/* flush map & render cache */
 		OUT_BATCH(MI_FLUSH | MI_WRITE_DIRTY_STATE |
@@ -139,7 +139,7 @@ I915DisplayVideoTextured(ScrnInfoPtr scrn,
 		if (!is_planar_fourcc(id)) {
 			FS_LOCALS(10);
 
-			BEGIN_BATCH(16);
+			ATOMIC_BATCH(16);
 			OUT_BATCH(_3DSTATE_PIXEL_SHADER_CONSTANTS | 4);
 			OUT_BATCH(0x0000001);	/* constant 0 */
 			/* constant 0: brightness/contrast */
@@ -200,7 +200,7 @@ I915DisplayVideoTextured(ScrnInfoPtr scrn,
 		} else {
 			FS_LOCALS(16);
 
-			BEGIN_BATCH(22 + 11 + 11);
+			ATOMIC_BATCH(22 + 11 + 11);
 			/* For the planar formats, we set up three samplers --
 			 * one for each plane, in a Y8 format.  Because I
 			 * couldn't get the special PLANAR_TO_PACKED
@@ -390,7 +390,7 @@ I915DisplayVideoTextured(ScrnInfoPtr scrn,
 		}
 
 		{
-			BEGIN_BATCH(2);
+			ATOMIC_BATCH(2);
 			OUT_BATCH(MI_FLUSH | MI_WRITE_DIRTY_STATE |
 				  MI_INVALIDATE_MAP_CACHE);
 			OUT_BATCH(0x00000000);
@@ -423,7 +423,7 @@ I915DisplayVideoTextured(ScrnInfoPtr scrn,
 			src_scale_x = ((float)src_w / width) / drw_w;
 			src_scale_y = ((float)src_h / height) / drw_h;
 
-			BEGIN_BATCH(8 + 12);
+			ATOMIC_BATCH(8 + 12);
 			OUT_BATCH(MI_NOOP);
 			OUT_BATCH(MI_NOOP);
 			OUT_BATCH(MI_NOOP);
diff --git a/src/i965_render.c b/src/i965_render.c
index 5e8e8749..8e907ebd 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -1162,7 +1162,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
 	 * rendering pipe
 	 */
 	{
-		BEGIN_BATCH(2);
+		ATOMIC_BATCH(2);
 		OUT_BATCH(MI_FLUSH |
 			  MI_STATE_INSTRUCTION_CACHE_FLUSH |
 			  BRW_MI_GLOBAL_SNAPSHOT_RESET);
@@ -1171,9 +1171,9 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
 	}
 	{
 		if (IS_IGDNG(intel))
-			BEGIN_BATCH(14);
+			ATOMIC_BATCH(14);
 		else
-			BEGIN_BATCH(12);
+			ATOMIC_BATCH(12);
 
 		/* Match Mesa driver setup */
 		if (IS_G4X(intel) || IS_IGDNG(intel))
@@ -1219,7 +1219,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
 	}
 	{
 		int pipe_ctrl;
-		BEGIN_BATCH(26);
+		ATOMIC_BATCH(26);
 		/* Pipe control */
 
 		if (IS_IGDNG(intel))
@@ -1332,7 +1332,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
 		}
 
 		if (IS_IGDNG(intel)) {
-			BEGIN_BATCH(mask ? 9 : 7);
+			ATOMIC_BATCH(mask ? 9 : 7);
 			/*
 			 * The reason to add this extra vertex element in the header is that
 			 * IGDNG has different vertex header definition and origin method to
@@ -1362,7 +1362,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
 				  (BRW_VFCOMPONENT_STORE_0 <<
 				   VE1_VFCOMPONENT_3_SHIFT));
 		} else {
-			BEGIN_BATCH(mask ? 7 : 5);
+			ATOMIC_BATCH(mask ? 7 : 5);
 			/* Set up our vertex elements, sourced from the single vertex buffer.
 			 * that will be set up later.
 			 */
@@ -1808,7 +1808,7 @@ i965_composite(PixmapPtr dest, int srcX, int srcY, int maskX, int maskY,
 	if (intel->needs_render_state_emit)
 		i965_emit_composite_state(scrn);
 
-	BEGIN_BATCH(12);
+	ATOMIC_BATCH(12);
 	OUT_BATCH(MI_FLUSH);
 	/* Set up the pointer to our (single) vertex buffer */
 	OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | 3);
diff --git a/src/i965_video.c b/src/i965_video.c
index 89d5eef8..6225aa48 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -779,7 +779,7 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * bind_bo, int n_src_surf)
 	urb_cs_start = urb_sf_start + urb_sf_size;
 	urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE;
 
-	BEGIN_BATCH(2);
+	ATOMIC_BATCH(2);
 	OUT_BATCH(MI_FLUSH |
 		  MI_STATE_INSTRUCTION_CACHE_FLUSH |
 		  BRW_MI_GLOBAL_SNAPSHOT_RESET);
@@ -788,9 +788,9 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * bind_bo, int n_src_surf)
 
 	/* brw_debug (scrn, "before base address modify"); */
 	if (IS_IGDNG(intel))
-		BEGIN_BATCH(14);
+		ATOMIC_BATCH(14);
 	else
-		BEGIN_BATCH(12);
+		ATOMIC_BATCH(12);
 	/* Match Mesa driver setup */
 	if (IS_G4X(intel) || IS_IGDNG(intel))
 		OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
@@ -844,7 +844,7 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * bind_bo, int n_src_surf)
 	else
 		pipe_ctl = BRW_PIPE_CONTROL_NOWRITE | BRW_PIPE_CONTROL_IS_FLUSH;
 
-	BEGIN_BATCH(38);
+	ATOMIC_BATCH(38);
 
 	OUT_BATCH(MI_NOOP);
 
@@ -1220,7 +1220,7 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn,
 
 		i965_emit_video_setup(scrn, bind_bo, n_src_surf);
 
-		BEGIN_BATCH(12);
+		ATOMIC_BATCH(12);
 		/* Set up the pointer to our vertex buffer */
 		OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | 3);
 		/* four 32-bit floats per vertex */