diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2011-04-07 15:09:30 +0100 |
|---|---|---|
| committer | Owain G. Ainsworth <oga@openbsd.org> | 2011-05-29 23:47:19 +0100 |
| commit | dba96684a5db6cbbbf9bb3f154c906a4ccb6b137 (patch) | |
| tree | 5bfe30a7e66736abedd1f56bad103150b9aa9143 /src | |
| parent | fde55b50c15ddc868a6bec5da37c50e61e6ffae7 (diff) | |
gen6: Invalidate texture cache
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
(cherry picked from commit 25521900df11bc71020ee80db2223f979bec5ec6)
Signed-off-by: Owain G. Ainsworth <oga@openbsd.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/i965_reg.h | 1 | ||||
| -rw-r--r-- | src/intel_batchbuffer.c | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/i965_reg.h b/src/i965_reg.h index 3953dab5..df41fba4 100644 --- a/src/i965_reg.h +++ b/src/i965_reg.h @@ -169,6 +169,7 @@ #define BRW_PIPE_CONTROL_DEPTH_STALL (1 << 13) #define BRW_PIPE_CONTROL_WC_FLUSH (1 << 12) #define BRW_PIPE_CONTROL_IS_FLUSH (1 << 11) +#define BRW_PIPE_CONTROL_TC_FLUSH (1 << 10) #define BRW_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8) #define BRW_PIPE_CONTROL_GLOBAL_GTT (1 << 2) #define BRW_PIPE_CONTROL_LOCAL_PGTT (0 << 2) diff --git a/src/intel_batchbuffer.c b/src/intel_batchbuffer.c index 332b2b3c..fcdd1084 100644 --- a/src/intel_batchbuffer.c +++ b/src/intel_batchbuffer.c @@ -157,6 +157,7 @@ void intel_batch_emit_flush(ScrnInfoPtr scrn) BEGIN_BATCH(4); OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2)); OUT_BATCH(BRW_PIPE_CONTROL_WC_FLUSH | + BRW_PIPE_CONTROL_TC_FLUSH | BRW_PIPE_CONTROL_NOWRITE); OUT_BATCH(0); /* write address */ OUT_BATCH(0); /* write data */ |