Align tiled pixmap height so we don't address beyond the end of our buffers (plus fix)

Original alignment patch
(cherry picked from commit 222b52ef16895823fbf3a0fc0be4eb23b930ed1b)
with subsequent "Fix math in the tiling alignment fix" squashed
(cherry picked from commit e8f0763d405a8152c74c28792c52fe12c1d41dd5)

5 files changed, 11 insertions, 9 deletions

diff --git a/src/i830.h b/src/i830.h
index 21c98f5b..bf61a7a8 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -619,6 +619,8 @@ typedef struct _I830Rec {
 #define I830PTR(p) ((I830Ptr)((p)->driverPrivate))
 
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
+#define ALIGN(i,m)	(((i) + (m) - 1) & ~((m) - 1))
+#define MIN(a,b)	((a) < (b) ? (a) : (b))
 
 #define I830_SELECT_FRONT	0
 #define I830_SELECT_BACK	1
diff --git a/src/i830_memory.c b/src/i830_memory.c
index cc9d376d..a73648b1 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -88,8 +88,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "i810_reg.h"
 #include "i915_drm.h"
 
-#define ALIGN(i,m)    (((i) + (m) - 1) & ~((m) - 1))
-
 /* Our hardware status area is just a single page */
 #define HWSTATUS_PAGE_SIZE GTT_PAGE_SIZE
 #define PWRCTX_SIZE GTT_PAGE_SIZE
diff --git a/src/i830_uxa.c b/src/i830_uxa.c
index 2050c485..fe0fb497 100644
--- a/src/i830_uxa.c
+++ b/src/i830_uxa.c
@@ -609,6 +609,13 @@ i830_uxa_create_pixmap (ScreenPtr screen, int w, int h, int depth, unsigned usag
 	if (tiling == I915_TILING_NONE) {
 	    size = stride * h;
 	} else {
+	    int aligned_h = h;
+	    if (tiling == I915_TILING_X)
+		aligned_h = ALIGN(h, 8);
+	    else
+		aligned_h = ALIGN(h, 32);
+	    assert(aligned_h >= h);
+
 	    stride = i830_get_fence_pitch(i830, stride, tiling);
 	    /* Round the object up to the size of the fence it will live in
 	     * if necessary.  We could potentially make the kernel allocate
@@ -616,8 +623,8 @@ i830_uxa_create_pixmap (ScreenPtr screen, int w, int h, int depth, unsigned usag
 	     * but this is easier and also keeps us out of trouble (as much)
 	     * with drm_intel_bufmgr_check_aperture().
 	     */
-	    size = i830_get_fence_size(i830, stride * h);
-	    assert(size >= stride * h);
+	    size = i830_get_fence_size(i830, stride * aligned_h);
+	    assert(size >= stride * aligned_h);
 	}
 
 	/* Fail very large allocations on 32-bit systems.  Large BOs will
diff --git a/src/i965_render.c b/src/i965_render.c
index eeb23e12..1a8075bc 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -251,8 +251,6 @@ i965_check_composite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
 
 }
 
-#define ALIGN(i,m)    (((i) + (m) - 1) & ~((m) - 1))
-#define MIN(a,b) ((a) < (b) ? (a) : (b))
 #define BRW_GRF_BLOCKS(nreg)    ((nreg + 15) / 16 - 1)
 
 /* Set up a default static partitioning of the URB, which is supposed to
diff --git a/src/i965_video.c b/src/i965_video.c
index 805b33f4..46a461f7 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -131,9 +131,6 @@ static const uint32_t ps_kernel_planar_static_gen5[][4] = {
 #include "exa_wm_write.g4b.gen5"
 };
 
-#define ALIGN(i,m)    (((i) + (m) - 1) & ~((m) - 1))
-#define MIN(a,b) ((a) < (b) ? (a) : (b))
-
 static uint32_t float_to_uint (float f) {
     union {uint32_t i; float f;} x;
     x.f = f;