diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2013-07-26 09:35:06 +0100 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2013-07-28 14:49:07 +0100 |
commit | 45d4e8dcf9aee37015b1ee026997ed4dabdf112e (patch) | |
tree | c140efa6a28d80266849d08d5ea368419e95c977 /xvmc/shader/mc/block_clear.g4i | |
parent | ab28526ea43728fb675448515e1519a970fb5f56 (diff) |
uxa: Clear up the common intel directory
Move all the UXA backend specifc files into their own subdirectory.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'xvmc/shader/mc/block_clear.g4i')
-rw-r--r-- | xvmc/shader/mc/block_clear.g4i | 140 |
1 files changed, 140 insertions, 0 deletions
diff --git a/xvmc/shader/mc/block_clear.g4i b/xvmc/shader/mc/block_clear.g4i new file mode 100644 index 00000000..ce12f3b5 --- /dev/null +++ b/xvmc/shader/mc/block_clear.g4i @@ -0,0 +1,140 @@ +/* + * Copyright © 2008 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Author: + * Zou Nan hai <nanhai.zou@intel.com> + * + */ + +and.nz (1) null g2.0<1,1,1>UD 0x1UD{align1}; +(f0) jmpi direct_idct; +add (1) g2.8<1>UD g76.8<1,1,1>UD 0UD{align1}; +send (16) 0 g3.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g4.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g5.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g6.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g7.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g8.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g9.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g10.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g11.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g12.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g13.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g14.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g15.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g16.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g17.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g18.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g19.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g20.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g21.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g22.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g23<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g24.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g25.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +add (1) g2.8<1>UD g2.8<1,1,1>UD 32UD {align1}; +send (16) 0 g26.0<1>UD g2<16,16,1>UD read(3, 0, 2, 0) mlen 1 rlen 1 { align1 }; +direct_idct: + +and.nz (1) null g76.12<1,1,1>UW 0x20UW {align1}; +(f0) jmpi next_block; +mov (8) g3.0<1>UW 0UW {align1}; +mov (8) g4.0<1>UW 0UW {align1}; +mov (8) g5.0<1>UW 0UW {align1}; +mov (8) g6.0<1>UW 0UW {align1}; +mov (8) g7.0<1>UW 0UW {align1}; +mov (8) g8.0<1>UW 0UW {align1}; +mov (8) g9.0<1>UW 0UW {align1}; +mov (8) g10.0<1>UW 0UW {align1}; +next_block: + +and.nz (1) null g1.12<1,1,1>UW 0x10UW {align1}; +(f0) jmpi next_field; +mov (8) g3.16<1>UW 0UW {align1}; +mov (8) g4.16<1>UW 0UW {align1}; +mov (8) g5.16<1>UW 0UW {align1}; +mov (8) g6.16<1>UW 0UW {align1}; +mov (8) g7.16<1>UW 0UW {align1}; +mov (8) g8.16<1>UW 0UW {align1}; +mov (8) g9.16<1>UW 0UW {align1}; +mov (8) g10.16<1>UW 0UW {align1}; +next_field: +and.nz (1) null g1.12<1,1,1>UW 0x8UW {align1}; +(f0) jmpi next_field; +mov (8) g11.0<1>UW 0UW {align1}; +mov (8) g12.0<1>UW 0UW {align1}; +mov (8) g13.0<1>UW 0UW {align1}; +mov (8) g14.0<1>UW 0UW {align1}; +mov (8) g15.0<1>UW 0UW {align1}; +mov (8) g16.0<1>UW 0UW {align1}; +mov (8) g17.0<1>UW 0UW {align1}; +mov (8) g18.0<1>UW 0UW {align1}; +next_field: +and.nz (1) null g1.12<1,1,1>UW 0x4UW {align1}; +(f0) jmpi next_field; +mov (8) g11.16<1>UW 0UW {align1}; +mov (8) g12.16<1>UW 0UW {align1}; +mov (8) g13.16<1>UW 0UW {align1}; +mov (8) g14.16<1>UW 0UW {align1}; +mov (8) g15.16<1>UW 0UW {align1}; +mov (8) g16.16<1>UW 0UW {align1}; +mov (8) g17.16<1>UW 0UW {align1}; +mov (8) g18.16<1>UW 0UW {align1}; +next_field: + +and.nz (1) null g1.12<1,1,1>UW 0x2UW {align1}; +(f0) jmpi next_field; +mov (16) g19.0<1>UW 0UW {align1}; +mov (16) g20.0<1>UW 0UW {align1}; +mov (16) g21.0<1>UW 0UW {align1}; +mov (16) g22.0<1>UW 0UW {align1}; +next_field: + +and.nz (1) null g1.12<1,1,1>UW 0x1UW {align1}; +(f0) jmpi next_field; +mov (16) g23.0<1>UW 0UW {align1}; +mov (16) g24.0<1>UW 0UW {align1}; +mov (16) g25.0<1>UW 0UW {align1}; +mov (16) g26.0<1>UW 0UW {align1}; +next_field: |