diff options
| -rw-r--r-- | src/intel_driver.h | 2 | ||||
| -rw-r--r-- | src/intel_module.c | 7 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/intel_driver.h b/src/intel_driver.h index ac02cc73..b7190620 100644 --- a/src/intel_driver.h +++ b/src/intel_driver.h @@ -229,6 +229,8 @@ #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A #define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A +#define PCI_CHIP_VALLEYVIEW_PO 0x0f30 + #endif #define I85X_CAPID 0x44 diff --git a/src/intel_module.c b/src/intel_module.c index 65a91b1c..bc0b6d25 100644 --- a/src/intel_module.c +++ b/src/intel_module.c @@ -103,6 +103,10 @@ static const struct intel_device_info intel_ivybridge_info = { .gen = 70, }; +static const struct intel_device_info intel_valleyview_info = { + .gen = 70, +}; + static const struct intel_device_info intel_haswell_info = { .gen = 75, }; @@ -192,6 +196,7 @@ static const SymTabRec _intel_chipsets[] = { {PCI_CHIP_HASWELL_CRW_S_GT1, "Haswell CRW Server (GT1)" }, {PCI_CHIP_HASWELL_CRW_S_GT2, "Haswell CRW Server (GT2)" }, {PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, "Haswell CRW Server (GT2+)" }, + {PCI_CHIP_VALLEYVIEW_PO, "ValleyView PO board" }, {-1, NULL} }; #define NUM_CHIPSETS (sizeof(_intel_chipsets) / sizeof(_intel_chipsets[0])) @@ -301,6 +306,8 @@ static const struct pci_id_match intel_device_match[] = { INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ), INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_PO, &intel_valleyview_info ), + INTEL_DEVICE_MATCH (PCI_MATCH_ANY, &intel_generic_info ), { 0, 0, 0 }, }; |