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-rw-r--r--src/i830_display.c128
-rw-r--r--src/i830_display.h1
2 files changed, 78 insertions, 51 deletions
diff --git a/src/i830_display.c b/src/i830_display.c
index fa2d94e8..39a535bd 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -769,8 +769,9 @@ i830PipeHasType (xf86CrtcPtr crtc, int type)
#if 1
#define i830PllInvalid(s) { /* ErrorF (s) */; return FALSE; }
-#endif
+#else
#define i830PllInvalid(s) { ErrorF (s) ; return FALSE; }
+#endif
/**
* Returns whether the given set of divisors are valid for a given refclk with
* the given outputs.
@@ -1491,7 +1492,6 @@ static void ironlake_fdi_link_train(xf86CrtcPtr crtc)
{
ScrnInfoPtr scrn = crtc->scrn;
intel_screen_private *intel = intel_get_screen_private(scrn);
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn);
I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
int pipe = intel_crtc->pipe;
int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
@@ -1581,55 +1581,40 @@ static void ironlake_fdi_link_train(xf86CrtcPtr crtc)
ErrorF("FDI train done\n");
}
-static void igdng_crtc_dpms(xf86CrtcPtr crtc, int mode)
+static void
+ironlake_crtc_enable(xf86CrtcPtr crtc)
{
- ScrnInfoPtr scrn = crtc->scrn;
- intel_screen_private *intel = intel_get_screen_private(scrn);
- I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn);
- int pipe = intel_crtc->pipe;
- int plane = intel_crtc->plane;
- int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
- int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
- int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
- int dspbase_reg = (plane == 0) ? DSPABASE : DSPBBASE;
- int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
- int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
- int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
- int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
- int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
- int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
- int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
- int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
- int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
- int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
- int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
- int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
- int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
- int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
- int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
- int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
- int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
- int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
- int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
- int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
- uint32_t temp;
- int tries = 5, i, j, n;
- uint32_t pipe_bpc;
+ ScrnInfoPtr scrn = crtc->scrn;
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+ I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
+ int pipe = intel_crtc->pipe;
+ int plane = intel_crtc->plane;
+ int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
+ int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
+ int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
+ int dspbase_reg = (plane == 0) ? DSPABASE : DSPBBASE;
+ int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
+ int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
+ int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
+ int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
+ int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
+ int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
+ int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
+ int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
+ int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
+ int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
+ int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
+ int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
+ int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
+ int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
+ int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
+ int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
+ int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
+ int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
+ uint32_t temp, pipe_bpc;
- if (intel_crtc->pipe != intel_crtc->plane)
- FatalError("pipe/plane mismatch, aborting\n");
-
- temp = INREG(pipeconf_reg);
- pipe_bpc = temp & PIPE_BPC_MASK;
-
- /* XXX: When our outputs are all unaware of DPMS modes other than off
- * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
- */
- switch (mode) {
- case DPMSModeOn:
- case DPMSModeStandby:
- case DPMSModeSuspend:
+ temp = INREG(pipeconf_reg);
+ pipe_bpc = temp & PIPE_BPC_MASK;
/* XXX no LVDS port force */
if (i830PipeHasType(crtc, I830_OUTPUT_LVDS)) {
@@ -1753,8 +1738,30 @@ static void igdng_crtc_dpms(xf86CrtcPtr crtc, int mode)
ErrorF("DPMS on done\n");
- break;
- case DPMSModeOff:
+}
+
+void
+ironlake_crtc_disable(xf86CrtcPtr crtc)
+{
+ ScrnInfoPtr scrn = crtc->scrn;
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+ I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
+ int pipe = intel_crtc->pipe;
+ int plane = intel_crtc->plane;
+ int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
+ int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
+ int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
+ int dspbase_reg = (plane == 0) ? DSPABASE : DSPBBASE;
+ int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
+ int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
+ int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
+ int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
+ int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
+ uint32_t temp, pipe_bpc;
+ int n;
+
+ temp = INREG(pipeconf_reg);
+ pipe_bpc = temp & PIPE_BPC_MASK;
ErrorF("Plane disable\n");
temp = INREG(dspcntr_reg);
@@ -1893,7 +1900,26 @@ static void igdng_crtc_dpms(xf86CrtcPtr crtc, int mode)
ErrorF("DPMS off done\n");
/* Wait for the clocks to turn off. */
usleep(150);
+}
+static void igdng_crtc_dpms(xf86CrtcPtr crtc, int mode)
+{
+ I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
+
+ if (intel_crtc->pipe != intel_crtc->plane)
+ FatalError("pipe/plane mismatch, aborting\n");
+
+ /* XXX: When our outputs are all unaware of DPMS modes other than off
+ * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
+ */
+ switch (mode) {
+ case DPMSModeOn:
+ case DPMSModeStandby:
+ case DPMSModeSuspend:
+ ironlake_crtc_enable(crtc);
+ break;
+ case DPMSModeOff:
+ ironlake_crtc_disable(crtc);
break;
}
}
diff --git a/src/i830_display.h b/src/i830_display.h
index f1975316..90d584ad 100644
--- a/src/i830_display.h
+++ b/src/i830_display.h
@@ -33,6 +33,7 @@ void i830WaitForVblank(ScrnInfoPtr scrn);
void i830DescribeOutputConfiguration(ScrnInfoPtr scrn);
void i830_set_new_crtc_bo(ScrnInfoPtr scrn);
void i830_crtc_disable(xf86CrtcPtr crtc, Bool disable_pipe);
+void ironlake_crtc_disable(xf86CrtcPtr crtc);
xf86CrtcPtr i830GetLoadDetectPipe(xf86OutputPtr output, DisplayModePtr mode,
int *dpms_mode);
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-12 13:28:19 +0000