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-rw-r--r--src/brw_defines.h7
-rw-r--r--src/brw_structs.h6
-rw-r--r--src/i965_render.c7
-rw-r--r--src/i965_video.c15
4 files changed, 34 insertions, 1 deletions
diff --git a/src/brw_defines.h b/src/brw_defines.h
index 0df2491c..e580a8f4 100644
--- a/src/brw_defines.h
+++ b/src/brw_defines.h
@@ -469,6 +469,13 @@
#define BRW_BORDER_COLOR_MODE_DEFAULT 0
#define BRW_BORDER_COLOR_MODE_LEGACY 1
+#define HSW_SCS_ZERO 0
+#define HSW_SCS_ONE 1
+#define HSW_SCS_RED 4
+#define HSW_SCS_GREEN 5
+#define HSW_SCS_BLUE 6
+#define HSW_SCS_ALPHA 7
+
#define BRW_TEXCOORDMODE_WRAP 0
#define BRW_TEXCOORDMODE_MIRROR 1
#define BRW_TEXCOORDMODE_CLAMP 2
diff --git a/src/brw_structs.h b/src/brw_structs.h
index f4dc927d..20c2f857 100644
--- a/src/brw_structs.h
+++ b/src/brw_structs.h
@@ -1659,7 +1659,11 @@ struct gen7_surface_state
struct {
unsigned int resource_min_lod:12;
- unsigned int pad0:16;
+ unsigned int pad0:4;
+ unsigned int shader_chanel_select_a:3;
+ unsigned int shader_chanel_select_b:3;
+ unsigned int shader_chanel_select_g:3;
+ unsigned int shader_chanel_select_r:3;
unsigned int alpha_clear_color:1;
unsigned int blue_clear_color:1;
unsigned int green_clear_color:1;
diff --git a/src/i965_render.c b/src/i965_render.c
index 30fef572..f7b21c8b 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -1392,6 +1392,13 @@ gen7_set_picture_surface_state(intel_screen_private *intel,
ss->ss2.width = pixmap->drawable.width - 1;
ss->ss3.pitch = intel_pixmap_pitch(pixmap) - 1;
+ if (IS_HSW(intel)) {
+ ss->ss7.shader_chanel_select_r = HSW_SCS_RED;
+ ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
+ ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
+ ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
+ }
+
dri_bo_emit_reloc(intel->surface_bo,
read_domains, write_domain,
0,
diff --git a/src/i965_video.c b/src/i965_video.c
index bba282dd..58b62221 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -510,6 +510,13 @@ static void gen7_create_dst_surface_state(ScrnInfoPtr scrn,
dest_surf_state.ss3.pitch = intel_pixmap_pitch(pixmap) - 1;
+ if (IS_HSW(intel)) {
+ dest_surf_state.ss7.shader_chanel_select_r = HSW_SCS_RED;
+ dest_surf_state.ss7.shader_chanel_select_g = HSW_SCS_GREEN;
+ dest_surf_state.ss7.shader_chanel_select_b = HSW_SCS_BLUE;
+ dest_surf_state.ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
+ }
+
dri_bo_subdata(surf_bo,
offset, sizeof(dest_surf_state),
&dest_surf_state);
@@ -525,6 +532,7 @@ static void gen7_create_src_surface_state(ScrnInfoPtr scrn,
drm_intel_bo *surface_bo,
uint32_t offset)
{
+ intel_screen_private * const intel = intel_get_screen_private(scrn);
struct gen7_surface_state src_surf_state;
memset(&src_surf_state, 0, sizeof(src_surf_state));
@@ -547,6 +555,13 @@ static void gen7_create_src_surface_state(ScrnInfoPtr scrn,
src_surf_state.ss3.pitch = src_pitch - 1;
+ if (IS_HSW(intel)) {
+ src_surf_state.ss7.shader_chanel_select_r = HSW_SCS_RED;
+ src_surf_state.ss7.shader_chanel_select_g = HSW_SCS_GREEN;
+ src_surf_state.ss7.shader_chanel_select_b = HSW_SCS_BLUE;
+ src_surf_state.ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
+ }
+
dri_bo_subdata(surface_bo,
offset, sizeof(src_surf_state),
&src_surf_state);