diff options
| -rw-r--r-- | src/i830.h | 5 | ||||
| -rw-r--r-- | src/i830_batchbuffer.c | 3 | ||||
| -rw-r--r-- | src/i830_driver.c | 7 | ||||
| -rw-r--r-- | src/i830_uxa.c | 7 | ||||
| -rw-r--r-- | src/i915_render.c | 27 |
5 files changed, 43 insertions, 6 deletions
@@ -295,6 +295,7 @@ typedef struct intel_screen_private { CloseScreenProcPtr CloseScreen; + void (*vertex_flush) (struct intel_screen_private *intel); void (*batch_flush_notify) (ScrnInfoPtr scrn); uxa_driver_t *uxa_driver; @@ -357,6 +358,9 @@ typedef struct intel_screen_private { uint32_t dst_format; } i915_render_state; + uint32_t prim_offset; + uint32_t prim_count; + /* 965 render acceleration state */ struct gen4_render_state *gen4_render_state; @@ -474,6 +478,7 @@ Bool i915_prepare_composite(int op, PicturePtr sourcec, PicturePtr mask, PixmapPtr maskPixmap, PixmapPtr destPixmap); void i915_composite(PixmapPtr dest, int srcX, int srcY, int maskX, int maskY, int dstX, int dstY, int w, int h); +void i915_vertex_flush(intel_screen_private *intel); void i915_batch_flush_notify(ScrnInfoPtr scrn); void i830_batch_flush_notify(ScrnInfoPtr scrn); /* i965_render.c */ diff --git a/src/i830_batchbuffer.c b/src/i830_batchbuffer.c index c23b0b85..0fe81d03 100644 --- a/src/i830_batchbuffer.c +++ b/src/i830_batchbuffer.c @@ -165,6 +165,9 @@ void intel_batch_submit(ScrnInfoPtr scrn) if (intel->batch_used == 0) return; + if (intel->vertex_flush) + intel->vertex_flush(intel); + /* Emit a padding dword if we aren't going to be quad-word aligned. */ if ((intel->batch_used & 4) == 0) { *(uint32_t *) (intel->batch_ptr + intel->batch_used) = MI_NOOP; diff --git a/src/i830_driver.c b/src/i830_driver.c index db8af063..6ec6f519 100644 --- a/src/i830_driver.c +++ b/src/i830_driver.c @@ -1227,11 +1227,12 @@ I830ScreenInit(int scrnIndex, ScreenPtr screen, int argc, char **argv) return FALSE; } - if (IS_I965G(intel)) + if (IS_I965G(intel)) { intel->batch_flush_notify = i965_batch_flush_notify; - else if (IS_I9XX(intel)) + } else if (IS_I9XX(intel)) { + intel->vertex_flush = i915_vertex_flush; intel->batch_flush_notify = i915_batch_flush_notify; - else + } else intel->batch_flush_notify = i830_batch_flush_notify; miInitializeBackingStore(screen); diff --git a/src/i830_uxa.c b/src/i830_uxa.c index d4028959..f68ec701 100644 --- a/src/i830_uxa.c +++ b/src/i830_uxa.c @@ -467,6 +467,10 @@ static void i830_uxa_done_copy(PixmapPtr dest) void i830_done_composite(PixmapPtr dest) { ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum]; + intel_screen_private *intel = intel_get_screen_private(scrn); + + if (intel->vertex_flush) + intel->vertex_flush(intel); i830_debug_flush(scrn); } @@ -1051,6 +1055,9 @@ Bool i830_uxa_init(ScreenPtr screen) intel->uxa_driver->uxa_major = 1; intel->uxa_driver->uxa_minor = 0; + intel->prim_offset = 0; + intel->prim_count = 0; + /* Solid fill */ intel->uxa_driver->check_solid = i830_uxa_check_solid; intel->uxa_driver->prepare_solid = i830_uxa_prepare_solid; diff --git a/src/i915_render.c b/src/i915_render.c index 59d92481..7c204b62 100644 --- a/src/i915_render.c +++ b/src/i915_render.c @@ -708,6 +708,9 @@ static void i915_emit_composite_setup(ScrnInfoPtr scrn) FS_END(); } + + intel->prim_offset = 0; + intel->prim_count = 0; } /* Emit the vertices for a single composite rectangle. @@ -850,9 +853,10 @@ i915_emit_composite_primitive(PixmapPtr dest, num_floats = 3 * per_vertex; - ATOMIC_BATCH(1 + num_floats); + ATOMIC_BATCH(num_floats); + + intel->prim_count += num_floats; - OUT_BATCH(PRIM3D_INLINE | PRIM3D_RECTLIST | (num_floats - 1)); OUT_BATCH_F(intel->dst_coord_adjust + dstX + w); OUT_BATCH_F(intel->dst_coord_adjust + dstY + h); if (! intel->render_source_is_solid) { @@ -926,13 +930,30 @@ i915_composite(PixmapPtr dest, int srcX, int srcY, int maskX, int maskY, if (intel->needs_render_state_emit) i915_emit_composite_setup(scrn); + if (intel->prim_offset == 0) { + intel->prim_offset = intel->batch_used; + ATOMIC_BATCH(1); + OUT_BATCH(PRIM3D_INLINE | PRIM3D_RECTLIST); + ADVANCE_BATCH(); + } + i915_emit_composite_primitive(dest, srcX, srcY, maskX, maskY, dstX, dstY, w, h); intel_batch_end_atomic(scrn); } -void i915_batch_flush_notify(ScrnInfoPtr scrn) +void +i915_vertex_flush(intel_screen_private *intel) +{ + if (intel->prim_offset) { + *(uint32_t *) (intel->batch_ptr + intel->prim_offset) |= intel->prim_count - 1; + intel->prim_offset = 0; + } +} + +void +i915_batch_flush_notify(ScrnInfoPtr scrn) { intel_screen_private *intel = intel_get_screen_private(scrn); |