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-rw-r--r--src/i830.h15
-rw-r--r--src/i830_hwmc.c2
-rw-r--r--src/i830_memory.c181
-rw-r--r--src/i915_hwmc.c8
4 files changed, 69 insertions, 137 deletions
diff --git a/src/i830.h b/src/i830.h
index 07b6c8de..7a64f00e 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -93,12 +93,6 @@ typedef struct _I830OutputRec I830OutputRec, *I830OutputPtr;
#define ALWAYS_SYNC 0
#define ALWAYS_FLUSH 0
-enum tile_format {
- TILE_NONE,
- TILE_XMAJOR,
- TILE_YMAJOR
-};
-
#define PITCH_NONE 0
/** Record of a linear allocation in the aperture. */
@@ -115,7 +109,7 @@ struct _i830_memory {
*/
unsigned long size;
- enum tile_format tiling;
+ uint32_t tiling_mode;
/** Pitch value in bytes for tiled surfaces */
unsigned int pitch;
@@ -130,7 +124,6 @@ struct _i830_memory {
/** @} */
dri_bo *bo;
- uint32_t alignment;
uint32_t gem_name;
};
@@ -351,8 +344,7 @@ Bool i830_allocator_init(ScrnInfoPtr scrn, unsigned long size);
void i830_allocator_fini(ScrnInfoPtr scrn);
i830_memory *i830_allocate_memory(ScrnInfoPtr scrn, const char *name,
unsigned long size, unsigned long pitch,
- unsigned long alignment, int flags,
- enum tile_format tile_format);
+ int flags, uint32_t tile_format);
void i830_describe_allocations(ScrnInfoPtr scrn, int verbosity,
const char *prefix);
void i830_reset_allocations(ScrnInfoPtr scrn);
@@ -376,7 +368,7 @@ int i830_pad_drawable_width(int width, int cpp);
Bool i830_bind_all_memory(ScrnInfoPtr scrn);
unsigned long i830_get_fence_size(intel_screen_private *intel, unsigned long size);
unsigned long i830_get_fence_pitch(intel_screen_private *intel, unsigned long pitch,
- int format);
+ uint32_t tiling_mode);
void i830_set_max_gtt_map_size(ScrnInfoPtr scrn);
i830_memory *i830_allocate_framebuffer(ScrnInfoPtr scrn);
@@ -486,7 +478,6 @@ extern const int I830CopyROP[16];
/* Flags for memory allocation function */
#define NEED_PHYSICAL_ADDR 0x00000001
-#define ALIGN_BOTH_ENDS 0x00000002
#define ALLOW_SHARING 0x00000010
#define DISABLE_REUSE 0x00000020
diff --git a/src/i830_hwmc.c b/src/i830_hwmc.c
index c365dd5f..3471524a 100644
--- a/src/i830_hwmc.c
+++ b/src/i830_hwmc.c
@@ -147,7 +147,7 @@ Bool intel_xvmc_init_batch(ScrnInfoPtr scrn)
if (!i830_allocate_xvmc_buffer(scrn, "[XvMC] batch buffer",
&(xvmc_driver->batch), size,
- ALIGN_BOTH_ENDS))
+ 0))
return FALSE;
if (drmAddMap(intel->drmSubFD,
diff --git a/src/i830_memory.c b/src/i830_memory.c
index 957f5983..f32abc2a 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -122,12 +122,13 @@ unsigned long i830_get_fence_size(intel_screen_private *intel, unsigned long siz
* calculate that here.
*/
unsigned long
-i830_get_fence_pitch(intel_screen_private *intel, unsigned long pitch, int format)
+i830_get_fence_pitch(intel_screen_private *intel, unsigned long pitch,
+ uint32_t tiling_mode)
{
unsigned long i;
- unsigned long tile_width = (format == I915_TILING_Y) ? 128 : 512;
+ unsigned long tile_width = (tiling_mode == I915_TILING_Y) ? 128 : 512;
- if (format == TILE_NONE)
+ if (tiling_mode == I915_TILING_NONE)
return pitch;
/* 965 is flexible */
@@ -140,18 +141,6 @@ i830_get_fence_pitch(intel_screen_private *intel, unsigned long pitch, int forma
return i;
}
-/**
- * On some chips, pitch width has to be a power of two tile width, so
- * calculate that here.
- */
-static unsigned long i830_get_fence_alignment(intel_screen_private *intel, unsigned long size)
-{
- if (IS_I965G(intel))
- return 4096;
- else
- return i830_get_fence_size(intel, size);
-}
-
static Bool
i830_check_display_stride(ScrnInfoPtr scrn, int stride, Bool tiling)
{
@@ -298,22 +287,53 @@ void i830_allocator_fini(ScrnInfoPtr scrn)
intel->memory_list = NULL;
}
-static i830_memory *i830_allocate_memory_bo(ScrnInfoPtr scrn, const char *name,
- unsigned long size,
- unsigned long pitch,
- unsigned long align, int flags,
- enum tile_format tile_format)
+/* Allocates video memory at the given size, pitch, alignment and tile format.
+ *
+ * The memory will be bound automatically when the driver is in control of the
+ * VT. When the kernel memory manager is available and compatible with flags
+ * (that is, flags doesn't say that the allocation must include a physical
+ * address), that will be used for the allocation.
+ *
+ * flags:
+ * - NEED_PHYSICAL_ADDR: Allocates the memory physically contiguous, and return
+ * the bus address for that memory.
+ * - NEED_NON-STOLEN: don't allow any part of the memory allocation to lie
+ * within stolen memory
+ * - NEED_LIFETIME_FIXED: don't allow the buffer object to move throughout
+ * the entire Screen lifetime. This means not using buffer objects, which
+ * get their offsets chosen at each EnterVT time.
+ */
+i830_memory *i830_allocate_memory(ScrnInfoPtr scrn, const char *name,
+ unsigned long size, unsigned long pitch,
+ int flags, uint32_t tiling_mode)
{
- intel_screen_private *intel = intel_get_screen_private(scrn);
i830_memory *mem;
- uint32_t bo_tiling_mode = I915_TILING_NONE;
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+ uint32_t requested_tiling_mode = tiling_mode;
int ret;
+ /* Manage tile alignment and size constraints */
+ if (tiling_mode != I915_TILING_NONE) {
+ /* Only allocate page-sized increments. */
+ size = ALIGN(size, GTT_PAGE_SIZE);
+
+ /* Check for maximum tiled region size */
+ if (IS_I9XX(intel)) {
+ if (size > MB(128))
+ return NULL;
+ } else {
+ if (size > MB(64))
+ return NULL;
+ }
+
+ /* round to size necessary for the fence register to work */
+ size = i830_get_fence_size(intel, size);
+ }
+
assert((flags & NEED_PHYSICAL_ADDR) == 0);
/* Only allocate page-sized increments. */
size = ALIGN(size, GTT_PAGE_SIZE);
- align = i830_get_fence_alignment(intel, size);
mem = xcalloc(1, sizeof(*mem));
if (mem == NULL)
@@ -325,7 +345,7 @@ static i830_memory *i830_allocate_memory_bo(ScrnInfoPtr scrn, const char *name,
return NULL;
}
- mem->bo = dri_bo_alloc(intel->bufmgr, name, size, align);
+ mem->bo = dri_bo_alloc(intel->bufmgr, name, size, GTT_PAGE_SIZE);
if (!mem->bo) {
xfree(mem->name);
@@ -337,32 +357,15 @@ static i830_memory *i830_allocate_memory_bo(ScrnInfoPtr scrn, const char *name,
mem->offset = -1;
mem->end = -1;
mem->size = size;
- mem->alignment = align;
- mem->tiling = tile_format;
mem->pitch = pitch;
- switch (tile_format) {
- case TILE_XMAJOR:
- bo_tiling_mode = I915_TILING_X;
- break;
- case TILE_YMAJOR:
- bo_tiling_mode = I915_TILING_Y;
- break;
- case TILE_NONE:
- default:
- bo_tiling_mode = I915_TILING_NONE;
- break;
- }
-
- ret = drm_intel_bo_set_tiling(mem->bo, &bo_tiling_mode, pitch);
- if (ret != 0
- || (bo_tiling_mode == I915_TILING_NONE
- && tile_format != TILE_NONE)) {
+ ret = drm_intel_bo_set_tiling(mem->bo, &tiling_mode, pitch);
+ if (ret != 0 || tiling_mode != requested_tiling_mode) {
xf86DrvMsg(scrn->scrnIndex, X_ERROR,
"Failed to set tiling on %s: %s\n", mem->name,
ret == 0 ? "rejected by kernel" : strerror(errno));
- mem->tiling = TILE_NONE;
}
+ mem->tiling_mode = tiling_mode;
if (flags & DISABLE_REUSE)
drm_intel_bo_disable_reuse(mem->bo);
@@ -377,57 +380,6 @@ static i830_memory *i830_allocate_memory_bo(ScrnInfoPtr scrn, const char *name,
return mem;
}
-/* Allocates video memory at the given size, pitch, alignment and tile format.
- *
- * The memory will be bound automatically when the driver is in control of the
- * VT. When the kernel memory manager is available and compatible with flags
- * (that is, flags doesn't say that the allocation must include a physical
- * address), that will be used for the allocation.
- *
- * flags:
- * - NEED_PHYSICAL_ADDR: Allocates the memory physically contiguous, and return
- * the bus address for that memory.
- * - ALIGN_BOTH_ENDS: after choosing the alignment, align the end offset to
- * @alignment as well.
- * - NEED_NON-STOLEN: don't allow any part of the memory allocation to lie
- * within stolen memory
- * - NEED_LIFETIME_FIXED: don't allow the buffer object to move throughout
- * the entire Screen lifetime. This means not using buffer objects, which
- * get their offsets chosen at each EnterVT time.
- */
-i830_memory *i830_allocate_memory(ScrnInfoPtr scrn, const char *name,
- unsigned long size, unsigned long pitch,
- unsigned long alignment, int flags,
- enum tile_format tile_format)
-{
- i830_memory *mem;
- intel_screen_private *intel = intel_get_screen_private(scrn);
-
- /* Manage tile alignment and size constraints */
- if (tile_format != TILE_NONE) {
- /* Only allocate page-sized increments. */
- size = ALIGN(size, GTT_PAGE_SIZE);
-
- /* Check for maximum tiled region size */
- if (IS_I9XX(intel)) {
- if (size > MB(128))
- return NULL;
- } else {
- if (size > MB(64))
- return NULL;
- }
-
- /* round to size necessary for the fence register to work */
- size = i830_get_fence_size(intel, size);
- alignment = i830_get_fence_alignment(intel, size);
- }
-
- return i830_allocate_memory_bo(scrn, name, size,
- pitch, alignment, flags, tile_format);
-
- return mem;
-}
-
void
i830_describe_allocations(ScrnInfoPtr scrn, int verbosity, const char *prefix)
{
@@ -453,9 +405,9 @@ i830_describe_allocations(ScrnInfoPtr scrn, int verbosity, const char *prefix)
char phys_suffix[32] = "";
char *tile_suffix = "";
- if (mem->tiling == TILE_XMAJOR)
+ if (mem->tiling_mode == I915_TILING_X)
tile_suffix = " X tiled";
- else if (mem->tiling == TILE_YMAJOR)
+ else if (mem->tiling_mode == I915_TILING_Y)
tile_suffix = " Y tiled";
xf86DrvMsgVerb(scrn->scrnIndex, X_INFO, verbosity,
@@ -472,9 +424,9 @@ i830_describe_allocations(ScrnInfoPtr scrn, int verbosity, const char *prefix)
for (mem = intel->bo_list; mem != NULL; mem = mem->next) {
char *tile_suffix = "";
- if (mem->tiling == TILE_XMAJOR)
+ if (mem->tiling_mode == I915_TILING_X)
tile_suffix = " X tiled";
- else if (mem->tiling == TILE_YMAJOR)
+ else if (mem->tiling_mode == I915_TILING_Y)
tile_suffix = " Y tiled";
xf86DrvMsgVerb(scrn->scrnIndex, X_INFO, verbosity,
@@ -527,11 +479,10 @@ i830_memory *i830_allocate_framebuffer(ScrnInfoPtr scrn)
intel_screen_private *intel = intel_get_screen_private(scrn);
unsigned int pitch = scrn->displayWidth * intel->cpp;
unsigned long minspace;
- int align;
long size, fb_height;
int flags;
i830_memory *front_buffer = NULL;
- enum tile_format tile_format = TILE_NONE;
+ uint32_t tiling_mode;
flags = ALLOW_SHARING | DISABLE_REUSE;
@@ -548,30 +499,21 @@ i830_memory *i830_allocate_framebuffer(ScrnInfoPtr scrn)
size = ROUND_TO_PAGE(pitch * fb_height);
- if (intel->tiling)
- tile_format = TILE_XMAJOR;
-
- if (!IsTileable(scrn, pitch))
- tile_format = TILE_NONE;
+ if (intel->tiling && IsTileable(scrn, pitch))
+ tiling_mode = I915_TILING_X;
+ else
+ tiling_mode = I915_TILING_NONE;
- if (!i830_check_display_stride(scrn, pitch, tile_format != TILE_NONE)) {
+ if (!i830_check_display_stride(scrn, pitch,
+ tiling_mode != I915_TILING_NONE)) {
xf86DrvMsg(scrn->scrnIndex, X_ERROR,
"Front buffer stride %d kB "
"exceed display limit\n", pitch / 1024);
return NULL;
}
- /* Attempt to allocate it tiled first if we have page flipping on. */
- if (tile_format != TILE_NONE) {
- /* XXX: probably not the case on 965 */
- if (IS_I9XX(intel))
- align = MB(1);
- else
- align = KB(512);
- } else
- align = KB(64);
front_buffer = i830_allocate_memory(scrn, "front buffer", size,
- pitch, align, flags, tile_format);
+ pitch, flags, tiling_mode);
if (front_buffer == NULL) {
xf86DrvMsg(scrn->scrnIndex, X_ERROR,
@@ -599,8 +541,7 @@ static Bool i830_allocate_cursor_buffers(ScrnInfoPtr scrn)
intel->cursor_mem_argb[i] =
i830_allocate_memory(scrn, "ARGB cursor",
HWCURSOR_SIZE_ARGB, PITCH_NONE,
- GTT_PAGE_SIZE, DISABLE_REUSE,
- TILE_NONE);
+ DISABLE_REUSE, I915_TILING_NONE);
if (!intel->cursor_mem_argb[i])
return FALSE;
@@ -667,7 +608,7 @@ Bool i830_allocate_xvmc_buffer(ScrnInfoPtr scrn, const char *name,
int flags)
{
*buffer = i830_allocate_memory(scrn, name, size, PITCH_NONE,
- GTT_PAGE_SIZE, flags, TILE_NONE);
+ flags, I915_TILING_NONE);
if (!*buffer) {
xf86DrvMsg(scrn->scrnIndex, X_ERROR,
diff --git a/src/i915_hwmc.c b/src/i915_hwmc.c
index e1a45b50..8be52f26 100644
--- a/src/i915_hwmc.c
+++ b/src/i915_hwmc.c
@@ -316,7 +316,7 @@ static Bool i915_allocate_xvmc_buffers(ScrnInfoPtr scrn,
I915XvMCContextPriv * ctxpriv)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
- int flags = ALIGN_BOTH_ENDS;
+ int flags = 0;
/* on 915G/GM, load indirect can only use physical address...sigh */
if (IS_I915G(intel) || IS_I915GM(intel))
@@ -354,7 +354,7 @@ static Bool i915_allocate_xvmc_buffers(ScrnInfoPtr scrn,
if (!i830_allocate_xvmc_buffer(scrn, "[XvMC]Correction Data Buffer",
&(ctxpriv->mcCorrdata), 512 * 1024,
- ALIGN_BOTH_ENDS)) {
+ 0)) {
return FALSE;
}
@@ -595,7 +595,7 @@ static int i915_xvmc_create_surface(ScrnInfoPtr scrn, XvMCSurfacePtr pSurf,
if (!i830_allocate_xvmc_buffer(scrn, "XvMC surface",
&(sfpriv->surface), bufsize,
- ALIGN_BOTH_ENDS)) {
+ 0)) {
xf86DrvMsg(scrn->scrnIndex, X_ERROR,
"[XvMC] i915 : Failed to allocate XvMC surface space!\n");
xfree(sfpriv);
@@ -687,7 +687,7 @@ static int i915_xvmc_create_subpict(ScrnInfoPtr scrn, XvMCSubpicturePtr pSubp,
if (!i830_allocate_xvmc_buffer(scrn, "XvMC surface",
&(sfpriv->surface), bufsize,
- ALIGN_BOTH_ENDS)) {
+ 0)) {
xf86DrvMsg(scrn->scrnIndex, X_ERROR,
"[XvMC] I915XvMCCreateSurface: Failed to allocate XvMC surface space!\n");
xfree(sfpriv);
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-05 18:22:55 +0000