diff options
Diffstat (limited to 'src/i810_reg.h')
| -rw-r--r-- | src/i810_reg.h | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/src/i810_reg.h b/src/i810_reg.h index 191ddb2a..9f78eb1d 100644 --- a/src/i810_reg.h +++ b/src/i810_reg.h @@ -2214,6 +2214,12 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # define SVBLANK_INT_STATUS (1 << 2) # define VBLANK_INT_STATUS (1 << 1) # define OREG_UPDATE_STATUS (1 << 0) +#define PIPE_BPC_MASK (7 << 5) /* Ironlake */ +#define PIPE_8BPC (0 << 5) +#define PIPE_10BPC (1 << 5) +#define PIPE_6BPC (2 << 5) +#define PIPE_12BPC (3 << 5) + #define DSPARB 0x70030 @@ -2350,6 +2356,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* IGDNG */ #define DISPPLANE_X_TILE (1<<10) #define DISPPLANE_LINEAR (0<<10) +#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) #define DSPABASE 0x70184 /* IGDNG */ @@ -3067,6 +3074,10 @@ typedef enum { #define PFA_CTL_1 0x68080 #define PFB_CTL_1 0x68880 #define PF_ENABLE (1<<31) +#define PFA_WIN_SZ 0x68074 +#define PFB_WIN_SZ 0x68874 +#define PFA_WIN_POS 0x68070 +#define PFB_WIN_POS 0x68870 #define PFA_WIN_POS 0x68070 #define PFB_WIN_POS 0x68870 @@ -3118,6 +3129,10 @@ typedef enum { #define GTIIR 0x44018 #define GTIER 0x4401c + +#define DISP_ARB_CTL 0x45000 +#define DISP_TILE_SURFACE_SWIZZLING (1<<13) + /* PCH */ /* south display engine interrupt */ @@ -3189,8 +3204,11 @@ typedef enum { #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) #define DREF_SSC_SOURCE_DISABLE (0<<11) #define DREF_SSC_SOURCE_ENABLE (2<<11) +#define DREF_SSC_SOURCE_MASK (2<<11) #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) +#define DREF_NONSPREAD_CK505_ENABLE (1<<9) #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) +#define DREF_NONSPREAD_SOURCE_MASK (2<<9) #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) #define DREF_SSC4_DOWNSPREAD (0<<6) @@ -3302,6 +3320,7 @@ typedef enum { #define FDI_DP_PORT_WIDTH_X2 (1<<19) #define FDI_DP_PORT_WIDTH_X3 (2<<19) #define FDI_DP_PORT_WIDTH_X4 (3<<19) +#define FDI_DP_PORT_WIDTH_MASK (7<<19) #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) /* IGDNG: hardwired to 1 */ #define FDI_TX_PLL_ENABLE (1<<14) @@ -3320,6 +3339,7 @@ typedef enum { #define FDI_10BPC (1<<16) #define FDI_6BPC (2<<16) #define FDI_12BPC (3<<16) +#define FDI_BPC_MASK (3<<16) #define FDI_LINK_REVERSE_OVERWRITE (1<<15) #define FDI_DMI_LINK_REVERSE_MASK (1<<14) #define FDI_RX_PLL_ENABLE (1<<13) @@ -3406,6 +3426,48 @@ typedef enum { #define HDMIC 0xe1150 #define HDMID 0xe1160 #define PCH_LVDS 0xe1180 +#define LVDS_DETECTED (1 << 1) + +#define PCH_DP_B 0xe4100 +#define PCH_DP_C 0xe4200 +#define PCH_DP_D 0xe4200 + +#define BLC_PWM_CPU_CTL2 0x48250 +#define PWM_ENABLE (1 << 31) +#define PWM_PIPE_A (0 << 29) +#define PWM_PIPE_B (1 << 29) +#define BLC_PWM_CPU_CTL 0x48254 + +#define BLC_PWM_PCH_CTL1 0xc8250 +#define PWM_PCH_ENABLE (1 << 31) +#define PWM_POLARITY_ACTIVE_LOW (1 << 29) +#define PWM_POLARITY_ACTIVE_HIGH (0 << 29) +#define PWM_POLARITY_ACTIVE_LOW2 (1 << 28) +#define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28) + +#define BLC_PWM_PCH_CTL2 0xc8254 + +#define PCH_PP_STATUS 0xc7200 +#define PCH_PP_CONTROL 0xc7204 +#define EDP_FORCE_VDD (1 << 3) +#define EDP_BLC_ENABLE (1 << 2) +#define PANEL_POWER_RESET (1 << 1) +#define PANEL_POWER_OFF (0 << 0) +#define PANEL_POWER_ON (1 << 0) +#define PCH_PP_ON_DELAYS 0xc7208 +#define EDP_PANEL (1 << 30) +#define PCH_PP_OFF_DELAYS 0xc720c +#define PCH_PP_DIVISOR 0xc7210 + +#define DE_POWER1 0x42400 +#define WM0_PIPE_A 0x45100 +#define WM0_PIPE_B 0x45104 +#define WM1 0x45108 +#define WM2 0x4510C +#define WM3 0x45110 +#define WM1S 0x45120 + + #define AUD_CONFIG 0x62000 #define AUD_DEBUG 0x62010 |