diff options
Diffstat (limited to 'src/intel_driver.h')
| -rw-r--r-- | src/intel_driver.h | 36 |
1 files changed, 24 insertions, 12 deletions
diff --git a/src/intel_driver.h b/src/intel_driver.h index 4b05e255..32f623b2 100644 --- a/src/intel_driver.h +++ b/src/intel_driver.h @@ -201,9 +201,12 @@ #define PCI_CHIP_HASWELL_S_GT1 0x040A #define PCI_CHIP_HASWELL_S_GT2 0x041A #define PCI_CHIP_HASWELL_S_GT3 0x042A -#define PCI_CHIP_HASWELL_GT1_RSVD 0x040E -#define PCI_CHIP_HASWELL_GT2_RSVD 0x041E -#define PCI_CHIP_HASWELL_GT3_RSVD 0x042E +#define PCI_CHIP_HASWELL_B_GT1 0x040B +#define PCI_CHIP_HASWELL_B_GT2 0x041B +#define PCI_CHIP_HASWELL_B_GT3 0x042B +#define PCI_CHIP_HASWELL_E_GT1 0x040E +#define PCI_CHIP_HASWELL_E_GT2 0x041E +#define PCI_CHIP_HASWELL_E_GT3 0x042E #define PCI_CHIP_HASWELL_SDV_D_GT1 0x0C02 #define PCI_CHIP_HASWELL_SDV_D_GT2 0x0C12 @@ -214,9 +217,12 @@ #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A #define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A -#define PCI_CHIP_HASWELL_SDV_GT1_RSVD 0x0C0E -#define PCI_CHIP_HASWELL_SDV_GT2_RSVD 0x0C1E -#define PCI_CHIP_HASWELL_SDV_GT3_RSVD 0x0C2E +#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0E +#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1E +#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2E +#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E +#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E +#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E #define PCI_CHIP_HASWELL_ULT_D_GT1 0x0A02 #define PCI_CHIP_HASWELL_ULT_D_GT2 0x0A12 @@ -227,9 +233,12 @@ #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A #define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A -#define PCI_CHIP_HASWELL_ULT_GT1_RSVD 0x0A0E -#define PCI_CHIP_HASWELL_ULT_GT2_RSVD 0x0A1E -#define PCI_CHIP_HASWELL_ULT_GT3_RSVD 0x0A2E +#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B +#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B +#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B +#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E +#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E +#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E #define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D02 #define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D12 @@ -240,9 +249,12 @@ #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A #define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A -#define PCI_CHIP_HASWELL_CRW_GT1_RSVD 0x0D0E -#define PCI_CHIP_HASWELL_CRW_GT2_RSVD 0x0D1E -#define PCI_CHIP_HASWELL_CRW_GT3_RSVD 0x0D2E +#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B +#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B +#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B +#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E +#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E +#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 #define PCI_CHIP_VALLEYVIEW_1 0x0f31 |